Cadence Design Systems, Inc.

Felipe Althoff

Habeeb Farah

Georgia Penido Safe

Thiago Radicchi Roque

Doron Bustan

Karam Abdelkader

Vincent Gregory Reynolds

Mirlaine Aparecida Crepalde

Yumi Monma

Fernanda Augusta Braga

Lucas Martins Chaves

Ayman Hanna

Pedro Bruno Neri Silva

Mariana Ferreira Marques

A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.

Method and system for sequential equivalence checking

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

System, method, and computer program product for determining suitability for formal verification

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San Jose, CA, United States of America

Felipe Althoff