Cadence Design Systems, Inc.

Felice Balarin

Michael Jude Meyer

Yosinori Watanabe

Yaron Kashai

Walter J Ghijsen

Evgueni Goldberg

David Van Campenhout

Sherry Solden

Stavros Tripakis

Viorica Simion

Abhinav Tallapally

Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state node name, an associated path annotation, and/or an associated hierarchical path. In an embodiment, a method to rename a state node based on a user-specified name includes using annotation information to locate a target state node and associating the target state node with the user-specified name or an automatically-created name based on the user-specified name. In an embodiment, a name specified for a state node can persist through successive runs of an HLS tool.

Annotations to identify objects in design generated by high level synthesis (HLS)

Disclosed are a method, system, and computer program product for implementing external domain independent modeling framework in a system design. In some embodiments, the method or system comprises importing an external model in an external format into the framework while substantially preserving some or all of the interpretation of the external model, determining a internal common representation for the external model within the framework, and displaying or storing the internal common representation in a tangible computer readable medium. In some embodiments, the method or system further comprises validating the accuracy of the internal common representation, determining an analysis or transformation capability for the framework, or outputting a first output model in a second external format. In various embodiments, the method or system requires no external tool compliance.

Method, system, and computer program product for implementing external domain independent modeling framework in a system design

An improved method and mechanism for verification of an electrical circuit design is provided. The method and system simultaneously provides the coverage advantage of formal verification with the scaling efficiencies of simulation. In one approach, the method and system generates an intelligent set of test vectors off a resolution proof. The intelligent set of test vectors can be used to simulate the circuit design for complete coverage without having to test the entire set of possible variable assignments for the CNF formula corresponding to the circuit design.

Method and mechanism for performing simulation off resolution proof

A general methodology for worst-case analysis of systems with discrete observable signals is disclosed. According to one embodiment, a signature &sgr; is chosen and a &sgr;-abstraction F is created, based on the system and the particular property to be analyzed. This procedure requires a user to facilitate the creation of an appropriate signature and &sgr;-abstraction. Next, for a given length of time T, a signature s is determined. From the signature s the worst-case boundary conditions are determined. The methodology may also be applied to timing analysis of embedded systems implemented on a single processor. The procedure calculates a time T which is an upper bound on the time a processor can be busy (i.e. busy period). Thus, for the busy-period analysis, the time T is no longer fixed. As in the first embodiment, a signature &sgr; is selected and a &sgr;-abstraction F is created. A workload function R is chosen, and a signature s and time T are calculated. The calculated time T is an upper bound on the length of a busy period for the given system.

Procedure for worst-case analysis of discrete systems

Efficient methods for verifying the timing behavior of a system in which various tasks are executed on a processor, and each task is enabled (i.e., becomes ready to execute) in response to the occurrence of an external event and/or the completion of another task. The methods are computationally efficient, requiring an execution time that is polynomial in the number of tasks in the system. The methods can be used in complementary fashion with more computationally intensive techniques for timing behavior verification, such as simulation or prototyping, by limiting the use of such techniques to those systems whose correctness is not proven by the methods.

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Berkeley, CA, United States of America

Felice Balarin