Yangtze Memory Technologies Co., Ltd.

Feifei Zhu

Youxin He

Jiaguo Li

Na Cao

Example memory systems, methods, and media for aggregating responses from memory systems to mitigate interrupt overhead in hosts coupled to the memory systems are disclosed. One example method includes receiving multiple commands from a host. Multiple responses are sent to the host at a time instant, where each of the responses is generated in a memory system during a time period and responsive to a respective one of the commands.

Response control in memory systems for reducing interrupt overhead

Implementations of the present disclosure disclose a memory controller and a control method thereof, a memory apparatus and a control method thereof, and a memory system and a control method thereof. The memory controller is coupled with at least one memory apparatus, and the memory apparatus includes a plurality of pages; the memory controller is configured to: receive a first command set, wherein the first command set includes at least one read command; when the first command set meets a first preset condition, enable a first read mode, wherein the first preset condition includes that the queue depth of the first command set is 1 or the total length of logical addresses in the first command set is less than or equal to a first threshold value; send demands corresponding to the first command set to the memory apparatus; and output data corresponding to the logical addresses in the first command set among all data of a first page sent by the memory apparatus, wherein the first page is a page, which corresponds to the logical addresses in the first command set, in the memory apparatus.

Memory controller and control method thereof, memory apparatus, and memory system that improve the balance of the read performance

In certain aspects, a memory system may include at least one memory device and a memory controller coupled to the at least one memory device. Each memory device may include an array of memory cells and a control logic coupled to the array of memory cells. The memory controller and the control logic of the memory device may be powered by a first power source having a first predetermined power consumption threshold. The array of memory cells of the memory device may be powered by a second power source having a second predetermined power consumption threshold. The memory controller may be configured to maintain a first queue of memory operations, wherein execution of the memory operations in the first queue causes power consumption from the first power source; maintain a second queue of memory operations, wherein execution of the memory operations in the second queue causes power consumption from the second power source; separately determine whether execution of subsequent memory operations in the first and second queues, respectively, would cause the corresponding first and second power sources to be overloaded; execute, based on the determination, the subsequent memory operation in the first or second queue that would not cause the corresponding first or second power source to be overloaded; and delay, based on the determination, the subsequent memory operation in the first or second queue that would cause the corresponding first or second power source to be overloaded.

Power management for a memory system

In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating total concurrent power consumption of executing a plurality of memory operations in parallel. The memory controller may also be configured to determine an addon power consumption value indicating additional power consumption of executing a subsequent memory operation. The memory controller may be further configured to determine whether a summation of the current and the addon power consumption values exceeds a predetermined power consumption threshold. After determining that the summation of the current and the addon power consumption values does not exceed the predetermined power consumption threshold, the memory controller may be configured to execute the subsequent memory operation in parallel with the plurality of memory operations.

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Wuhan, China

Feifei Zhu