Abb Schweiz Ag

Syntest Technologies, Inc.

Feifei Zhao

Cheng Li

Laung-Terng Wang

Shianling Wu

Zhigang Jiang

Hao-Jan Chao

Yichao Mao

Fangfang Li

Jianping Yan

Jinsong Liu

Lizhen Yu

Weijie Yan

The present application discloses an apparatus for mounting an O-ring to a work piece, which includes a body including a plurality of connecting holes for connecting a pressure source to the body; an annular groove formed on the body and adapted to receive the O-ring; and a plurality of air channels formed in the body, the plurality of air channels being in fluid communication with the annular groove and the plurality of connecting holes to provide negative pressure with the pressure source in the annular groove to suck the O-ring in the annular groove, the annular groove is coaxial with a groove formed on a surface of the work piece during the mounting so that the O-ring is dropped into the groove when the pressure source is disconnected from the body or provides positive pressure to the plurality of air channels.

Apparatuses and methods for separating, feeding and mounting O-rings

An apparatus for mounting an O-ring to a work piece, including: a plurality of picking components operable to move away from each other to contact and expand the O-ring to pick the O-ring or to move towards each other to release the O-ring; and a guiding component including a frustum portion arranged coaxially with a groove of the work piece, a large end face of the frustum portion arranged adjacent to an end surface of the work piece on which the groove is formed, wherein a diameter of the large end face is substantially same as an inner diameter of the groove, wherein the picking components are operable to release the O-ring onto a tapered surface of the frustum portion so that the O-ring is pushed into the groove along the tapered surface.

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N&#x3e;1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Multiple-capture DFT system to reduce peak capture power during self-test or scan test

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Shanghai, China

Feifei Zhao