Peking University

Boe Technology Group Co., Ltd.

Beijing Boe Optoelectronics Technology Co., Ltd.

Mediatek Singapore Pte. Ltd.

Hangzhou Synochip Technologies Co. Ltd

Feifei Zhang

Bin Gao

Xiaoyan Liu

Lifeng Liu

Jinfeng Kang

Bing Chen

Tao Chen

Xing Qin

Peiqiang Guan

Xiao Xin

Wenpeng Zhang

Xiaohui Yi

Zhaoliang Li

Boyun Qiu

A method for sidelink data retransmission can include receiving a first negative acknowledgement (NACK) at a base station (BS) from a receiver user equipment (Rx UE). The NACK corresponds to an original transmission of sidelink data over a sidelink from a transmitter user equipment (Tx UE). The method can further include selecting one or both of the BS and the Tx UE to perform a first retransmission of the sidelink data to the Rx UE. A method of sidelink synchronization can include selecting at a UE a timing reference with a highest priority among available sidelink synchronization timing references according to a rule indicating timing references listed from high priority to low priority: gNB or eNB; UE directly synchronized to gNB or eNB; UE in directly synchronized to gNB or eNB; GNSS; UE directly synchronized to GNSS; UE indirectly synchronized to GNSS; and remaining UEs.

Advanced V2X communication mechanism

A manufacturing method of an alignment layer and a manufacturing method of a display substrate are provided. The manufacturing method of the alignment layer includes: providing a display substrate on which a patterned structure is formed; applying the entire display substrate with wetting fluid, wherein the wetting fluid can be fused with alignment liquid; transferring the alignment liquid on the display substrate applied with the wetting fluid by a transfer roller; and curing the alignment liquid to form an alignment layer. The manufacturing method is used for producing the alignment layer on the display substrate.

Manufacturing method of alignment layer and manufacturing method of display substrate

A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line at its control terminal, to the resistive switching device at one terminal, and to a bit line at the other terminal; a word line decoder adapted to decode an input address signal to switch on the switching element in at least one of resistive switching memory units; and a driving circuit adapted to apply a voltage pulse whose front edge changes slowly across the resistive switching device by the bit line synchronously with the switching-on of the switching element. Using the scheme of the above embodiments, the durability characteristic of the resistive switching device can be improved, such as degradation of high-low resistance value window and the failure of the device with transition times can be reduced.

Resistive switching memory device and method for operating the same

The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a high resistance value to a low resistance value. The data value stored by the resistive-switching device is increased by '1' successively with a series of set pulses having a same pulse width and a same voltage amplitude being applied thereto. The data value stored by the resistive-switching device is set to '0' with a reset pulse being applied thereto, and meanwhile a data value stored by a higher-bit resistive-switching device is increased by &#x2018;1&#x2019; with a set pulse being applied thereto. In this way, multiary addition operation is implemented.

Resistive-switching device capable of implementing multiary addition operation and method for multiary addition operation

A neuron device includes a bottom electrode, a top electrode, and a layer of metal oxide variable resistance material sandwiched between the bottom electrode and the top electrode, in which the neuron device is switched to a normal state upon application of reset pulse, and is switched to an excitation state upon application of stimulus pulses. The neuron device has a comprehensive response to different amplitude, different width of a stimulus voltage pulse and different number of a sequence of stimulus pulses, and provides functionalities of a weighting section and a computing section. The neuron device has a simple structure, excellent scalability, quick speed, low operation voltage, and is compatible with the conventional silicon-based CMOS fabrication process, and thus suitable for mass production. The neuron device is capable of performing many biological functions and complex logic operations.

Three-layered neuron devices for neural network with reset voltage pulse

A multi-channel SPI interface memory controller disposed between a CPU and a multi-channel SPI interface memory is provided in the present invention. The multi-channel SPI interface memory controller comprises: a data path interface coupled to a bus of the CPU; a control path interface coupled to the bus of the CPU; a master controller coupled to the multi-channel SPI interface memory; a register bank disposed between the master controller and the control path interface, wherein the master controller is in signal coupling with the data path interface, and in signal coupling through the register bank with the control path interface. The inventive multi-channel SPI interface memory controller can support direct execution of a program on the SPI interface memory.

Method and apparatus for executing a program by an SPI interface memory

Growing community of inventors

Beijing, China

Feifei Zhang