Kilopass Technologies, Inc.

Fortemedia, Inc.

Kilopass Technology, Inc.

Klp International, Ltd.

Lattice Semiconductor Corporation

Fei Ye

Jack Zezhong Peng

David Fong

Michael David Fliesler

Jianguo Wang

Zhongshan Liu

Sho-Mo Chen

Harry Luan

Feng Yang

Zhongshang Liu

Methods and apparatus are disclosed for controlling power distribution during transitory power-up period of multi-domain electronic circuits that are supplied by multiple power supplies. The power distribution is controlled by self-regulating power control circuits that operate based on power-up sequencing requirements. Described embodiments of the invention illustrate examples of power-switch and power-switch controller circuits used as elements of the power control circuitry.

Power distribution control circuit for multi-power domain electronic circuits

Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.

Low power memory sub-system architecture

A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.

Combination field programmable gate array allowing dynamic reprogrammability

A method of programming a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises allowing current to flow through the data storage element until a predetermined current or voltage is detected. If the current or voltage exceeds a threshold, then the programming is deemed complete.

Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.

Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.

Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown

A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.

Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage

A programming circuit includes a wordline decoder, an adjustable voltage generator, and a column transistor. The programming circuit is useful in programming a memory cell comprised of a select transistor and a data storage element. The data storage element is programmed by a programming current. The amount of the programming current can be modulated by the column transistor, the select transistor, or the adjustable voltage generator.

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Cupertino, CA, United States of America

Fei Ye