Lenovo (beijing) Limited

Marvellworld Trade Ltd.

Beijing Lenovo Software Ltd.

Bitmain Technologies Limited

Marvell International Limited

Marvell Asia Pte., Ltd.

Microsoft Technology Licensing, LLC

Beijing Llvision Technology Co., Ltd.

Tsinghua University

Beijing Protgen Ltd.

Yantai Protgen Biotechnology Development Co., Ltd.

Fei Wu

Dehuan Meng

Hugh Walsh

Biing Long Shu

Xiaopan Zheng

Feijun Weng

Junfeng Liu

Lijun Wang

Yunfeng Pan

Zhenrong Zheng

Yi Zhang

Wei Liu

Bo Zhang

Donald Robert Pannell

Chunlei Zhao

Yongzhang Luo

Yan Fu

Guodong Chang

Chenggang Zou

Hongrui Zhang

Sangeeta Mudnal

Bin Yang

Xiaomin Song

Wujun Li

Xiangchao Liu

Gongyu Zhou

Donald Pannel

Michuan Li

Chuntao Lu

Dawei Cui

Provided are a chip power supply circuit and an electronic device, which relate to the field of power supply technologies. The chip power supply circuit includes: at least two chip domains, where the at least two chip domains are sequentially connected, and in two adjacent chip domains, a ground port of a previous-stage chip domain is connected to a primary power supply port of a next-stage chip domain; and at least one voltage conversion circuit, where in the two adjacent chip domains, the ground port of the previous-stage chip domain is connected to a secondary power supply port of the next-stage chip domain through a voltage conversion circuit of the at least one voltage conversion circuit, and the voltage conversion circuit is configured to output a target voltage to the secondary power supply port.

Chip power supply circuit and electronic device

The present application discloses a power supply circuit, a chip and an electronic device. The circuit comprises: a power module, configured to supply power to a computing chip in serial connection; a first power management module, connected with the power module and the computing chip, and configured to supply power to a core of the computing chip according to a voltage provided by the power module; and at least one second power management module, connected with the power module and the computing chip, and configured to supply power to at least one voltage domain of the computing chip according to the voltage provided by the power module correspondingly before the first power management module supplies power to the core.

Power supply circuit, chip, and electronic device

A chip power supply circuit and an electronic device are provided. The chip power supply circuit includes: one or more chips each comprising a first power supply pin and a second power supply pin; a first voltage regulator circuit connected to the first power supply pin of a corresponding chip of the one or more chips; and a second voltage regulator circuit, where the first power supply pin of the corresponding chip of the one or more chips is connected to the second power supply pin of the corresponding chip via the second voltage regulator circuit, and the second voltage regulator circuit is configured to convert the first voltage into a second voltage. The first voltage regulator circuit and the second voltage regulator circuit are respectively located on different sides of at least one of the one or more chips.

Provided are a chip, a series power supply circuit, a data processing device, and a computer server. The chip includes a plurality of units to be powered, the plurality of units to be powered are connected in parallel, and a voltage domain forms on each unit to be powered. Each unit to be powered is connected to a voltage regulation unit in series, and during power-on of the chip, the voltage regulation unit is regulated to control power-on time of the plurality of units to be powered.

Chip, series power supply circuit, data processing device, and computer server

The present disclosure provides a broadband cascaded splitting film array waveguide and a display system comprising the same. The cascaded splitting film array waveguide includes a plurality of glass substrates and a splitting film array, each film of the splitting film array is sandwiched between two adjacent glass substrates and consists of a plurality of H coatings and L coatings alternately arranged in sequence, wherein the H coatings are coatings made of a high refractive index material, the L coatings are coatings made of a low refractive index material, each film of the splitting film array has an even number of coatings, and thicknesses an, pn of the coatings of the film are selected based on the band width and angle of the light beam.

Broadband cascaded splitting film array waveguide and display system comprising same

A slab waveguide, comprising a plate having parallel surfaces and a cascade light splitting film. The plate is used for receiving and transmitting incident waveguide light which bears a transmitted image. The splitting film is disposed in the plate, intersects the upper and lower surface of the plate, and is used for reflecting the incident waveguide light out of the slab waveguide to form an actual image. In order to avoid mirror image coincidence, the waveguide needs to satisfy: |arcsin(n&#xd7;sin(90&#xb0;&#x2212;4a+b))&#x2212;arcsin(n&#xd7;sin(90&#xb0;&#x2212;2a&#x2212;b))1&#x3e;2&#x3c9;, wherein a is an inclined angle between the cascade light splitting film and the lower surface of the plate, b is an inclined angle between central image light of the incident waveguide light and the lower surface of the plate, &#x3c9; is an image display viewing angle of the transmitted image, and n is the refractive index of the plate.

Plate waveguide

According to an embodiment of the present disclosure, a virtual controller area network system includes first, second third controller area network (CAN) buses. A first CAN controller is coupled to the first and second CAN buses and is configured to route messages to and from the first and second CAN buses. A second CAN controller is coupled to the third CAN bus and is configured to route messages to and from the third CAN bus. A network bridging system is configured to route messages over a local area network between the first CAN controller and the second CAN controller.

Virtual controller area network

Embodiments described herein provide a method for an error logging mechanism operated with controller area network (CAN) buses within an Ethernet network. A first interrupt request indicative of a first error condition that occurs at the first CAN bus is received at an Ethernet bridge and from a first CAN controller connected to a first CAN bus. In response to the first interrupt request, the first interrupt request is serviced by retrieving, from a first error register at the first CAN controller, information relating to the first error condition. The information relating to the first error condition is encapsulated in a first frame in compliance with a layer 2 transport protocol for time-sensitive applications. The encapsulated first frame is then sent, via an Ethernet switch, to an error logging device installed at a location remote to the first CAN bus.

Systems and methods for an error logging mechanism at controller area network buses

Systems, methods, and apparatuses are provided herein for time-stamping a Controller Area Network ('CAN') bus message. Control circuitry (e.g., of a network bridge) may receive a CAN message, and may, in response to receiving the CAN message, generate a time stamp. The control circuitry may add an entry to a lookup table stored in memory, wherein the entry correlates a CAN message Identifier ('ID') corresponding to the CAN message with the time stamp. The control circuitry may encapsulate the CAN message and the time stamp, and may transmit the CAN message according to the time stamp.

Systems and methods for implementing a time-stamped controller area network (CAN) bus message

Systems and methods are provided for routing a message in a network. A bit length of an identifier field of a received message is identified. A lookup table is selected based on the bit length of the identifier field. The identifier field is used as a reference for the lookup table to identify a bus for the message, and the message is forwarded to the bus.

Control message routing structure for a controller area network

Aspects of the disclosure include a device for processing media samples. The device includes a frame decoder, a buffer, and a placement manager. The frame decoder is configured to receive a data frame from a source outside the device, extract from the data frame a first sample, and determine a first designated playback time of the first sample. The buffer has memory portions, and addresses of the memory portions are associated with a reference time and time increments of a local sampling period of the device. The placement manager is configured to store the first sample in a first memory portion of the buffer having a first address that is associated with a first time increment that most closely corresponds to the first designated playback time of the first sample.

Device and method for processing media samples

Aspects of the disclosure provide a method for scattering audio streams. The method can include receiving a set of audio data transmission signals indicating a format of audio data, determining a set of format parameters corresponding to the format of the audio data based on the set of audio data transmission signals, determining whether the set of format parameters are different from a set of previously determined format parameters, searching a lookup table for a build entry identified by the set of format parameters when the set of format parameters are different from the set of previously determined format parameters, and generating a media packet carrying audio samples of the audio data according to the build entry.

Scattering audio streams

Systems, methods, and apparatuses are described herein for implementing a switched Controller Area Network ('CAN'). In some embodiments, control circuitry of a bridge may receive a CAN message. The control circuitry may identify a first plurality of nodes to which the CAN message is addressed by comparing a virtual CAN bus identifier of the CAN message to entries of a virtual CAN bus lookup table, and may identify a second plurality of nodes to which the CAN message is addressed by comparing a message identifier ('ID') of the CAN message to entries of a message ID lookup table. The control circuitry may perform a logical AND operation between the first plurality of nodes and the second plurality of nodes, and may transmit the CAN message to a node that satisfies the logical AND operation.

Systems and methods for implementing a switched controller area network

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Beijing, China

Fei Wu