Scaleflux, Inc.

Alibaba Group Holding Limited

Marvell International Limited

Cadence Design Systems, Inc.

Marvellworld Trade Ltd.

Nio USA, Inc.

Fei Sun

Yang Liu

Hao Zhong

Tong Zhang

Wei Xu

Yen-kuang Chen

Minghai Qin

Siu-Hung Frederick Au

Jinjin He

Hyunsuk Shin

Chi Kong Lee

Yuhao Wang

Kai Xu

Chang Shu

Hongzhong Zheng

Shuangchen Li

Fei Xue

Dimin Niu

Tony Yoon

Wei Han

Bo Fu

Yuan Xie

ChengKuo Huang

Jungil Park

Mark Vernon

Sean Lee

Ka-Ming Keung

Xueshi Yang

William A Huffman

Siu-Hung Fred Au

Man Cheung

Dror E Maydan

Yen-Kuang Chen

Qinggang Zhou

Weifeng Zhang

Sachin P Ghanekar

Yuanwei Fang

Young-Ta Wu

Guoyang Chen

Jiangpeng Li

Chih-Ching Chen

Yingmin Li

James Sangkyu Kim

Kamran Turkoglu

Jingjun Chu

Kyle Satoshi Tsukamoto

Xipeng Shen

Grace Pao Yi Chen

Zhenzhen Wang

Tiansi Hu

A system and method for providing compression and error correction coding (ECC) in a solid-state drive (SSD). A method is provided that includes: determining whether a data item is to be written to flash memory using a general-purpose mode or a zero-padding mode: in response to a determination that a data item is to be written into flash memory using the zero-padding mode: padding the data item with an all-zero tail to form an LBA data block of a predefined size; performing ECC coding on the LBA block to generate an ECC codeword; removing the all-zero tail from the ECC codeword to generate a shortened ECC codeword; and storing the shortened ECC codeword in flash memory.

Solid-state drive with multimode compression and error correction

Embodiments of the disclosure provide devices and methods for performing a top-k function. The device can include: a memory comprising a plurality of register files for storing the data elements, the plurality of register files comprising a parent register file and a first child register file associated with the parent register file, wherein the parent register file is associated with: first interface circuitry configured for reading a first parent data element from the parent register file and receiving a first child data element and a second child data element from the first child register file; and first comparison circuitry configured for updating the parent register file and the first child register file based on the first parent data element, the first child data element, and the second child data element according to a given principle.

Performing a top-k function using a binary heap tree

Methods, apparatuses, and truncated multiplication circuitry for truncated multiplication are provided. Truncated multiplication circuitry includes a control register that includes a first section configured to store a first value representing truncating a most significant bit (MSB) of a partial product of a multiplier and a multiplicand, and a second section configured to store a value representing a truncation mode. The truncated multiplication circuitry also includes control circuitry configured to truncate the MSB of the partial product based on the truncation mode if the first section stores the first value. A method includes: in response to receiving a multiplier and a multiplicand, determining a partial product of the multiplier and the multiplicand; receiving a first value representing truncating a most significant bit (MSB) of the partial product and a value representing a truncation mode; and truncating the MSB of the partial product based on the truncation mode.

Low-power programmable truncated multiplication circuitry

Methods and systems are provided for implementing preprocessing operations and augmentation operations upon image datasets transformed to frequency domain representations, including decoding images of an image dataset to generate a frequency domain representation of the image dataset; performing a resizing operation based on resizing factors on the image dataset in a frequency domain representation; performing a reshaping operation based on reshaping factors on the image dataset in a frequency domain representation; and performing a cropping operation on the image dataset in a frequency domain representation. The methods and systems may further include performing an augmentation operation on the image dataset in a frequency domain representation. Methods and systems of the present disclosure may free learning models from computational overhead caused by transforming image datasets into frequency domain representations. Furthermore, computational overhead caused by inverse transformation operations is also alleviated.

Data preprocessing and data augmentation in frequency domain

A neural network, trained on a plurality of random size data samples, can receive a plurality of inference data samples including samples of different sizes. The neural network can generate feature maps of the plurality of inference data samples. Pooling can be utilized to generate feature maps having a fixed size. The fixed size feature maps can be utilized to generate an indication of a class for each of the plurality of inference data samples.

Variable input size techniques for neural networks

The present disclosure relates to a method and an apparatus for approximating non-linear function. In some embodiments, an exemplary processing unit includes: one or more registers for storing a lookup table (LUT) and one or more operation elements communicatively coupled with the one or more registers. The LUT includes a control state and a plurality of data entries. The one or more operation elements are configured to: receive an input operand; select one or more bits from the input operand; select a data entry from the plurality of data entries using the one or more bits; and determine an approximation value of a non-linear activation function for the input operand using the data entry.

Apparatuses and methods for approximating nonlinear function

An extensible processor can include an execution pipeline, one or more extensible control engines and architectural visible control states. The extensible processor can be configured to determine a control state of the one or more extensible control engines from the architectural visible control states. The extensible processor can be further configured to initiate execution of a given one of the extensible control engines when a control state in the architectural visible control states corresponding to the given one of the extensible control engines is enabled, wherein the given one of the extensible control engines comprises control input and control outputs based on one or more control transitions of an instruction. The extensible processor can also be further configured to output a result of execution of the given one of the extensible control engines to the architectural visible control states.

Custom instruction implemented finite state machine engines for extensible processors

A processor for sparse matrix calculation can include an on-chip memory, a cache, a gather/scatter engine and a core. The on-chip memory can be configured to store a first matrix or vector, and the cache can be configured to store a compressed sparse second matrix data structure. The compressed sparse second matrix data structure can include: a value array including non-zero element values of the sparse second matrix, where each entry includes a given number of element values; and a column index array where each entry includes the given number of offsets matching the value array. The gather/scatter engine can be configured to gather element values of the first matrix or vector using the column index array of the sparse second matrix. In a horizontal implementation, the gather/scatter engine can be configured to gather sets of element values from different sub-banks within a same row based on the column index array of the sparse matrix. In a vertical implementation, the gather/scatter engine can be configured to gather sets of element values from different rows based on the column index array of the sparse matrix. In a hybrid horizontal/vertical implementation, the gather/scatter engine can be configured to gather sets of element values from sets of rows and from different sub-banks within the same rows based on the column index array of the sparse matrix. The core can be configured to perform sparse matrix-matrix multiplication or sparse-matrix-vector multiplication using the gathered elements of the first matrix or vector and the value array of the compressed sparse second matrix.

Sparse matrix calculations untilizing ightly tightly coupled memory and gather/scatter engine

The present disclosure relates to a method for controlling execution of a GEMM operation on an accelerator comprising multiple computation units, a first memory device, and a second memory device. The method comprises determining an execution manner of the GEMM operation, the execution manner comprising partition information of the GEMM operation and computation unit allocation information of the partitioned GEMM operation; generating one or more instructions to compute the partitioned GEMM operation on one or more allocated computation units; and issuing the one or more instructions to at least one of a first queue and a second queue, which enables at least one of a first local controller and a second local controller to execute the one or more instructions, wherein the first local controller and the second local controller are configured to control data movement between the computation units, the first memory device, and the second memory device.

Programmable and hierarchical control of execution of GEMM operation on accelerator

Methods and systems are provided for implementing static channel filtering operations upon image datasets transformed to frequency domain representations, including decoding images of an image dataset to generate a frequency domain representation of the image dataset; discarding coefficient values of one or more particular frequency channels of each image of the image dataset in a frequency domain representation; and transporting the image dataset in a frequency domain representation to one or more special-purpose processor(s). Methods and systems of the present disclosure may enable a filtered image dataset to be input to a second layer of a learning model, bypassing a first layer, or may enable a learning model to be designed with a reduced-size first layer. This may achieve benefits such as reducing computational overhead and time of machine learning training and inference computations, reducing volume of image data input into the learning model, and reducing convergence time.

Static channel filtering in frequency domain

A system for processing encoded image components for artificial intelligence tasks. The system can include one or more compute units, one or more controllers and memory. The one or more controllers can include one or more micro-op schedulers and one or more channel switches. The one or more compute units can be configured to process components of the transformed domain image data according to one or more micro-operations for an artificial intelligence task. The one or more channel switches can be configured to selectively control the transfer of the components of transformed domain image data to the one or more compute units based on one or more gating flags. The one or more channel switches can also be configured to selectively control generation of the one or more micro-operations by the one or more micro-op schedulers based on the one or more gating flags.

Techniques to dynamically gate encoded image components for artificial intelligence tasks

A method of scheduling instructions in a processing system comprising a processing unit and one or more co-processors comprises dispatching a plurality of instructions from a master processor to a co-processor of the one or more co-processors, wherein each instruction of the plurality of instructions comprises one or more additional fields, wherein at least one field comprises grouping information operable to consolidate the plurality of instructions for decomposition, and wherein at least one field comprises control information. The method also comprises decomposing the plurality of instructions into a plurality of fine-grained instructions, wherein the control information comprises rules associated with decomposing the plurality of instructions into the plurality of fine-grained instructions. Further, the method comprises scheduling the plurality of fine-grained instructions to execute on the co-processor, wherein the scheduling is performed in a non-sequential order.

Methods of breaking down coarse-grained tasks for fine-grained task re-scheduling

A method according to embodiments includes: storing an entire hash table of a table R in memory of a computational storage device; storing a second table S in storage media of the computational storage device, the table R being smaller than the table S, wherein the hash JOIN operation is directed to combining a c-th column in the table S and a c-th column in the table R; wherein, for each row of the table S, the computational storage device configured to perform a method, including: applying a hash function to a value of the c-th column to provide a hash result; looking up the hash result in the hash table stored in the memory of the computational storage device; and if the hash result is found, sending the row of the table S and a corresponding row index of the table R to the host computing system.

Using in-storage computation to improve the performance of hash join for database and data analytics

Embodiments of the disclosure provide systems and methods for allocating memory space in a memory device. The system can include: a memory device for providing the memory space; and a compiler component configured for: receiving a request for allocating a data array having a plurality of data elements in the memory device, wherein each of the plurality of data elements has a logical address; generating an instruction for allocating memory space for the data array in the memory device based on the request; generating device addresses for the plurality of data elements in the memory device based on logical addresses of the plurality of data elements; and allocating the memory space for the data array in the memory device based on the device addresses and the instruction.

System and method for allocating memory space

A system for determining the importance of encoded image components for artificial intelligence tasks includes an image capture or storage unit, a processor and a communication interface. The processor can receive components of transformed domain image data from the one or more image capture or storage units across the communication interface. The processor can be configured to determine the relative importance of the components of the transformed domain image data for an artificial intelligence task.

Techniques for determining importance of encoded image components for artificial intelligence tasks

Growing community of inventors

Irvine, CA, United States of America

Fei Sun