Realtek Semiconductor Inc.

Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Fei Song

Chia-Liang (Leon) Lin

I-Chang Wu

Osama K A Shana'a

Chiyuan Lu

YuenHui Chee

James Han Wang

Keng Leong Fong

Chun-Geik Tan

Yuen Hui Chee

Toru Matsuura

Hsing-ting Yu

Salma Elabd

Osama Shana'a

Wenbo Xu

Osama K A SHANA'A

A clock distribution network includes receiving a remote voltage signal; transmitting the remote voltage signal into a local voltage signal using a current-mode transmission scheme that comprises a cascade of a voltage-to-current driver, a transmission line, a current buffer, and a LC (inductor-capacitor) tank; transmitting the local voltage signal into a first destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a first capacitively driven wire and a first inverter buffer; and transmitting the local voltage signal into a second destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a second capacitively driven wire and a second inverter buffer.

Method and apparatus for high speed clock distribution

A device includes a coil configured in a loop topology starting from a first end and extending to a second end, a pair of inward extension legs configured to extend from the first end and the second end toward an interior side of the coil to a third end and a fourth end, respectively, a pair of outward extension legs configured to extend from the first end and the second end toward an exterior side of the coil to a fifth end and a sixth end, respectively, a first capacitor configured to provide a capacitive coupling between the first end and the second end, a second capacitor configured to provide a capacitive coupling between the third end and the fourth end, and a third capacitor configured to provide a capacitive coupling between the fifth end and the sixth end.

LC tank circuit having improved resonant frequency stability and fabrication method thereof

A device having a substrate, a dielectric slab attached upon the substrate, a coil including a plurality of metal segments laid out on a first metal layer secured by the dielectric slab, the coil being substantially laterally symmetrical with respect to a central line from a top view perspective, and a shield laid out on a second metal layer secured by the dielectric slab and configured in a tree topology. The shield is substantially laterally symmetrical with respect to the central line from the top view perspective, the tree topology including a plurality of clusters of branches, wherein each of said plurality of clusters of branches is associated with a respective metal segment of the coil and includes a primary branch and at least one set of secondary branches that are branched from the primary branch, parallel to one another, and oriented at a substantially forty-five-degree angle with respect to the respective metal segment from the top view perspective.

High-Q integrated inductor and method thereof

A method includes generating a reference clock using a crystal oscillator; generating a first clock based on the reference clock using a clock multiplier unit, in which a frequency of the first clock is higher than a frequency of the reference clock by a clock multiplier factor; generating a second lock based on the first clock using a frequency multiplying circuit in accordance with a frequency multiplying signal, in which a frequency of the second clock is higher than the frequency of the first clock by a factor that is equal to either five fourths or three halves, depending on whether the frequency multiplying signal is in a first state or in a second state; dividing down the second clock by a factor of two to generate a first LO (local oscillator) signal; dividing down the first LO signal by a factor of two to generate a second LO signal.

Wide-band WLAN transceiver and method thereof

An apparatus includes a phase interpolator configured to receive a four-phase signal and output a six-phase signal, and a summing network configured to receive the six-phase signal and output a two-phase signal, wherein: a first phase, a third phase, and a fifth phase of the six-phase signal are summed to generate a second phase of the two-phase signal, while a second phase, a fourth phase, and a sixth phase of the six-phase signal are summed to generate a first phase of the two-phase signal.

Apparatus and method for frequency tripling

A method comprises: receiving a differential input signal; converting the differential input signal into a first transmitted current and a second transmitted current using a common-source differential pair biased by a bias current; launching the first transmitted current and the second transmitted current onto a first port of a differential transmission line; receiving a first received current and a second received current from a second port of the differential transmission line; buffering the first received current and the second received current into a first output current and a second output current, respectively, using a current buffer, wherein the current buffer comprises: a common-gate amplifier pair, a first cross-coupling network configured to provide a negative feedback on the input side of the current buffer to reduce an input impedance of the current buffer, and a second cross-coupling network configured to provide a positive feedback on the output side of the current buffer to boost an output impedance of the current buffer; and terminating the first output current and the second output current with a load to establish a differential output signal.

Method and apparatus for high speed clock transmission

Examples of front-end modules, apparatuses and methods for coupling compensation in a closed-loop digital pre-distortion (DPD) system are described. The closed-loop DPD circuit may include a PA and a loopback path. The PA may receive a PA input signal and amplify the PA input signal to provide a PA output signal proportional to a product of the PA input signal and a gain of the PA. The loopback path may receive the PA output signal to output a loopback signal. A forward coupling and a backward coupling may exist between the PA input signal and an output of the loopback path. The output of the loopback path may be proportional to a product of the PA output signal and a gain of the loopback path. The loopback path may include a coupling cancellation mechanism configured to cancel couplings between the PA input signal and the loopback signal.

Front-end module and coupling compensation for closed-loop digital pre-distortion system

Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

Wideband adaptive bias circuits for power amplifiers

A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET), a second PFET (PFET), a first NFET (NFET), and a second NFET (NFET). Sources of PFETand PFETare coupled to VDD. PFET's drain is coupled to an output lead. PFETacts as a current source. NFET's drain is coupled to PFET's drain and to PFET's gate. NFET's source is coupled to the output lead. NFET's source is coupled to ground. NFET's drain is coupled to NFET's source and to the output lead. NFET's gate is AC coupled to a first input lead. In a single-ended input example, NFET's gate is AC coupled NFET's drain. In a differential input example, NFET's gate is AC coupled to a second input lead. In another differential input example, PFETis not just a current source, but rather PFET's gate is AC coupled to the first input lead.

Wideband highly-linear low output impedance D2S buffer circuit

An amplifier receives an input signal with an input node, provides an output signal in response, and includes a main branch and an auxiliary branch. The auxiliary branch is coupled between the input node and a splitting node for input matching of the input node. The main branch, also coupled to the splitting node, has an output node of current mode, and is arranged to output the output signal at the output node. An associated receiver is also disclosed.

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San Jose, CA, United States of America

Fei Song