Huawei Technologies Co., Limited

Tsinghua University

Fei Qiao

Hai Chen

Fugui Xie

Han Xu

Xinjun Liu

Zheyu Liu

Qizhi Meng

Qi Wei

Weiyao Bi

Miao Zheng

Kaige Jia

A static random access memory SRAM unit and a related apparatus are provided, to reduce power consumption of an SRAM when the SRAM memory is accessed. The SRAM unit is located in an SRAM memory, and the SRAM memory includes an SRAM storage array including a plurality of SRAM units. The SRAM unit includes: a storage circuit, connected to each of a write circuit and a read circuit, and configured to store data; the write circuit, configured to write data into the storage circuit; and the read circuit, configured to: after a read enabling signal is valid, enable data on a read bit line connected to the SRAM unit to be the data stored in the storage circuit.

Static random access memory SRAM unit and related apparatus

A five-degree-of-freedom parallel mechanism and a series-parallel multi-degree-of-freedom equipment having the parallel mechanism are disclosed, and can machine complex components and parts as well as large structural parts and implement multi-degree-of-freedom numerical control machining, such as offsite maintenance of large equipment. The parallel mechanism includes: a rack; a movable platform; a first chain connected with the rack by at least two revolute pairs with axes intersecting with each other perpendicularly, and connected with the movable platform by at least two revolute pairs with axes intersecting with one another perpendicularly; a second chain having the same structure as the first chain; and a third chain including a main branch chain and two auxiliary branch chains, wherein the first chain, the second chain, and the third chain are separately connected between the rack and the movable platform.

Five-degree-of-freedom parallel mechanism and its extended equipment

An image processing apparatus, which includes a first physical computing circuit, configured to receive a plurality of first analog signals output by an image sensor, and perform a convolution operation on the plurality of first analog signals to obtain a second analog signal. The plurality of first analog signals are in a one-to-one correspondence with a plurality of pieces of pixel data of a to-be-recognized image. The first physical computing circuit comprises at least one multiplication circuit array and at least one subtraction circuit, the at least one multiplication circuit array is in a one-to-one correspondence with the at least one subtraction circuit, a multiplication circuit in each multiplication circuit array comprises a differential pair transistor, each multiplication circuit array implements the convolution operation on the plurality of first analog signals using a plurality of multiplication circuits and a corresponding subtraction circuit.

Image processing apparatus

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Beijing, China

Fei Qiao