Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Shanghai Xinjian Medical Co., Ltd.

Fei Liu

Hua Tang

Haifeng Yang

Benpeng Xun

Ben Peng Xun

Hai Yang

Xiao Yang Zhu

Chia Chi Yang

Meng Meng Guo

Mengmeng Guo

A customized surgical cutting guide mounted on a femur for TKR comprises a base having a plurality of cylinders located thereon, a pair of arms branching from a top of the base and each having a column located at a tip thereof, and a convex portion protruding from a bottom of the base and abutting against a corresponding portion of the femur. And wherein each cylinder has a through hole extending therethrough for allowing a kirschner pin to pass through, and wherein each column abuts against a corresponding portion of the femur and has a mounting hole extending therethrough for positioning the arms onto the corresponding positions of the femur, and wherein the arms, the cylinders, and the convex portion are located at the same side of the base.

Customized surgical cutting guide for total knee replacement and method for making thereof

A comparator and a successive approximation analog-to-digital converter are provided. The comparator includes a pre-operational amplifier, a latch, a level shift unit, and a reset unit. The pre-operational amplifier receives a to-be-compared signal, and outputs a first-stage amplification signal and a latch clock signal. The latch includes a first inverter circuit and a second inverter circuit, receives and compares the first-stage amplification signal, and outputs a comparison result signal. The level shift unit includes a first level shift circuit and a second level shift circuit, and generates a potential difference between working transistors in the first inverter circuit and the second inverter circuit, respectively. The reset unit includes a first reset circuit and a second reset circuit, and resets a voltage of a node where the level shift unit, the first inverter circuit and the second inverter circuit are coupled when the latch clock signal is at a low level.

Comparator and successive approximation analog-to-digital converter thereof

A patient-specific acetabular guide comprises a cup body, a plurality of alignment arms extending from the cup body and engaging periacetabular areas of a pelvis, and a supporting leg protruding from the cup body and abutting against a portion of an acetabular fossa. Each alignment arm has a fixing hole extending inclinedly therethrough to allow a Kirschner pin to pass through and enter the periacetabluar area of the pelvis for positing and orienting the acetabular guide on a predetermined location of an acetabulum.

Patient-specific accetabular guide

The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Circuit and method for generating clock-signals

The present disclosure provides asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

ASAR ADC circuit and conversion method thereof

The present disclosure provides an asynchronous successive approximation register analog-to-digital conversion (ASAR ADC) circuit, including: a comparator circuit, an XOR gate circuit, an ASAR logic circuit, a metastable state detection (MD) circuit, a capacitor, and a digital-to-analog converter (DAC) circuit. The comparator circuit has a first input terminal connected to an analog signal, a first output terminal of the comparator circuit respectively connected to a first input terminal of the ASAR circuit and a first input terminal of the XOR gate circuit, a second output terminal of the comparator circuit respectively connected to a second input terminal of the ASAR gate circuit and a second input terminal of the XOR gate circuit, and an enable signal input terminal connected to a control signal output terminal of the ASAR logic circuit. The XOR gate circuit has an output terminal connected to a third input terminal of the ASAR logic circuit.

Asynchronous successive approximation register analog-to-digital converter circuit and method for configuring the same

An oscillator circuit includes a voltage-controlled oscillator configured to output an AC output signal having a predetermined frequency, which changes due to temperature and fabrication process variations and a control voltage generating circuit configured to provide a voltage signal to the voltage-controlled oscillator to maintain the predetermined frequency by compensating for the temperature and fabrication process variations.

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Shanghai, China

Fei Liu