Agency for Science, Technology and Research

Fei Li

Kit Ho Melvin Chow

Wei He

Minghua Li

Sunny Yan Hwee Lua

Karim Ali Abdeltawwab Ahmed

Hongxin Yang

Yu Jiang

Various embodiments may relate to a memory cell. The memory cell may include a first cell electrode, a first insulator layer and a first magnetic free layer between the first cell electrode and the first insulator layer. The memory cell may also include a second cell electrode, a second insulator layer, and a second magnetic free layer between the second cell electrode and the second insulator layer. A magnetic pinned layer may be between the first insulator layer and the second insulator layer. A direction of magnetization of the first magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the first cell electrode. A direction of magnetization of the second magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the second cell electrode.

Memory cell, memory array, method of forming and operating memory cell

Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching layer includes at least one metal rich layer and at least one chalcogenide rich layer. The metal rich layer includes at least one of a metal or a metal compound, wherein metal content of the metal rich layer is greater than 50 at. %. The chalcogenide content of the chalcogenide rich layer is greater than 50 at. %.

Memory cell selector and method of operating memory cell

A method may include applying a first current through the memory element and a first selection component. The memory element and the first selection component may be located along a memory line. The method may also include measuring a first potential difference across the memory line. The method may further include applying a second current through a second selection component, wherein the second selection component is located along a dummy line, and measuring a second potential difference across the dummy line. The method may additionally include determining the resistance of the memory element based on the first potential difference and the second potential difference. The first selection component may be activated and the second selection component may be deactivated to apply the first current. The first selection component may be deactivated and the second selection component may be activated to apply the second current.

Methods and circuit arrangements for determining resistances

In various embodiments, a circuit arrangement may be provided including a data cell. The circuit arrangement may further include a first transistor and a second transistor. The first controlled electrode of the first transistor and the first controlled electrode of the second transistor may be coupled to the first electrode of the data cell. The second controlled electrode of the first transistor may be configured to electrically connect to a first reference voltage such that the first electrode of the data cell is electrically connected to the first reference voltage when the first transistor is activated. The second controlled electrode of the second transistor may be configured to electrically connect to a second reference voltage, such that the first electrode of the data cell is electrically connected to the second reference voltage when the second transistor is activated.

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Singapore, Singapore

Fei Li