Ati Technologies Ulc

Advanced Micro Devices Corporation

Fei Guo

Anwar Kashem

Julius Din

Sally Yeung

Mark Edward Frankovich

Feng Zhu

Rahul Kumar Agarwal

Milind S Bhagavat

Chih-Wei Chen

Neil McLellan

Angel E Socarras

Rahul Agarwal

Terence Cheung

Xiao Ling Shi

Wasim Ullah

Arsalan Alam

Wei He

Yuhong Zhang

Daniel Chung

Mark Frankovitch

A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.

Stacking power delivery device dies

A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form an anti-resonance tuning circuit has a first branch including a first inductance coupled to one of an IC die positive power supply conductor and an IC die negative power supply conductor, and a second branch coupled directly to a selected one of a carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

Anti-resonance structure for dampening die package resonance

Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

Interposer-based damping resistor

Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.

High density cross link die with polymer routing layer

A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form, an anti-resonance tuning circuit has a first node conductively coupled to one of the IC die's positive or negative power supply conductors, and a second node conductively coupled directly to a selected conductive structure on the carrier substrate. The anti-resonance tuning circuit includes a tuning capacitor, a tuning inductor, and optionally a dampening resistor coupled in series and having values sufficient to mitigate the die package resonance. In another form, impedance adjustment techniques are provided to connect and tune the anti-resonance tuning circuit to lower an impedance peak.

In one form, a data transmission system includes transmission and reception circuits. The transmission circuit includes a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage, a second driver having an input for receiving the I/O power supply voltage, an output, and a positive power supply terminal for receiving the I/O power supply voltage, and a third driver having an input for receiving the I/O ground voltage, an output, and a negative power supply terminal coupled to the I/O ground voltage. The reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of the second and third drivers, and receives a signal from the output of the first driver using the reference voltage.

Data transmission with power supply noise compensation

Method of manufacturing interposer-based damping resistor

A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.

Method and device for noise reduction in multi-frequency clocking environment

In an printed circuit board on which an integrated circuit die is mounted, an array of plated through holes (PTHs) are formed which include conductive power and ground PTH structures which are connected to provide power and ground reference voltages to the integrated circuit die, and isolated current sensing PTH structures which are formed within sensing proximity to the conductive power and ground PTH structures for sensing current switching activity in the conductive power and ground PTH structures by inductively converting dynamic current changes in the conductive power and ground PTH structures into a measurable voltage signal.

High bandwidth passive switching current sensor

Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor.

Under bump metallization for on-die capacitor

Various apparatus and methods of addressing crosstalk in a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first layer of a circuit board with a first signal trace and forming a second layer of the circuit board with a second signal trace. A first guard trace is formed on the first layer and offset laterally from the first signal trace but at least partially overlapping the second signal trace and a second guard trace is formed on the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace.

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Ottawa, Canada

Fei Guo