Intel Corporation

Fei Deng

Sanjib Sarkar

Yun He

Narender R Nagulapally

Senthil Arun Singaravelu

Pranali Shah

Eng Hun Ooi

Jeffrey Krieger

Jen-Tai Hsu

Serge Bedwani

Siang Lin Tan

Cliff C Lee

Kian Leong Phang

Scott T Gardiner

Jien Hau Ng

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

Unequalized clock data recovery for serial I/O receiver

A method, circuit, and system are disclosed. In one embodiment, the method comprises sending a step pulse across a serial advanced technology attachment (SATA) transmission line, determining the length of time the transmission line takes to charge from common mode voltage to supply voltage, and determining whether a device is connected to the SATA transmission line based on the length of the transmission line charge time.

Serial advanced technology attachment device presence detection and hot-plug in low power mode

Various embodiments provide a high speed serial transmitter that utilizes a current-mode driver comprising a main driver and a de-emphasis driver. The de-emphasis driver includes a first driver circuit and a complementary second driver circuit that is operably coupled with the first driver circuit. Collectively, the first driver circuit and its complementary second driver circuit work in concert to compensate to correct the lower output common-mode level in de-emphasized bits.

Common-mode noise-reduced output transmitter

A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers are adjacent. Other structures and methods are also described and claimed.

Method and apparatus to boost high-speed I/O signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces

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Folsom, CA, United States of America

Fei Deng