International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Samsung Electronics Co., Ltd.

Elpis Technologies Inc.

Tessera LLC

Terresa, Inc.

Fee Li Lie

Kangguo Cheng

Eric R Miller

Gauri V Karve

John Ryan Sporre

Marc Adam Bergendahl

Sivananda K Kanakasabapathy

Junli Wang

Bruce Bennett Doris

Brent A Anderson

Hong He

Huiming Bu

Lawrence Alfred Clevenger

Shogo Mochizuki

Chi-Chun Liu

Kamal Kumar Sikka

Ruilong Xie

Juntao Li

Dario Leonardo Goldfarb

Peng Xu

Soon-Cheon Seo

Robert Russell Robison

Ekmini Anuja De Silva

Hosadurga K Shobha

Tenko Yamashita

Terence B Hook

Robert C Wong

Edward J Nowak

Zhenxing Bi

Effendi Leobandung

Hsueh-Chung Chen

Andrew Mark Greene

Nicolas J Loubet

Oleg Gluschenkov

Michael Rizzolo

Matthew Earl Colburn

Yann Mignot

Chih-Chao Yang

Choonghyun Lee

Chen Zhang

Theodorus E Standaert

Ramachandra Divakaruni

Hemanth Jagannathan

Lars W Liebmann

Wenyu Xu

Shreesh Narasimha

Su Chen Fan

Kisik Choi

Sean Teehan

Stuart A Sieg

Jeffrey C Shearer

Indira P Seshadri

Donald Francis Canaperi

Leigh Anne H Clevenger

Cheng Chi

Nicole A Saulnier

Daniel A Corliss

Dinesh Gupta

Ryan O Jung

Derrick Liu

Mona Abdulkhaleg Ebrish

Dongbing Shao

Thamarai Selvi Devarajan

Isabel Cristina Chu

Yongan Xu

Byeong Yeol Kim

Deepika Priyadarshini

Allen H Gabor

Richard Anthony Conti

Chun Wing Yeung

Michael P Belyansky

Huimei Zhou

Jessica M Dechene

Sagarika Mukesh

Ravi K Bonam

Iqbal Rashid Saraf

Devika Sarkar Grant

Jay William Strane

Kevin R Winstel

Kisup Chung

Guillaume Bouche

Tara Lynn Astigarraga

Joshua M Rubin

Muthumanickam Sankarapandian

Scott David Halle

Raghavasimhan Sreenivasan

Somnath Ghosh

Yi Song

Linus Jang

Richard C Johnson

Robin Hsin Kuo Chao

Mahender Kumar

Xintuo Dai

Praveen Joseph

Russell Herbert Arndt

Siva Kanakasabapathy

Lei L Zhuang

Eric Miller

Cody John Murray

Alex Richard Hubbard

Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.

Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features

One or more systems, devices and/or methods provided herein relate to a circuit device having a modular or selectively designed interconnect structure with a plurality of conformal features. In the semiconductor realm, such achievements can allow for fabrication of a device with sub 18 nanometer (nm) or lesser pitch between adjacent and/or parallel lines of the interconnect structure. A device can comprise a semiconductor device having an interconnect structure having a first set of parallel lines and a second set of parallel lines, where the lines of the first set can be arranged in a transverse direction to the lines of the second set. The lines of the first set can be disposed orthogonally to the lines of the second set. The first second sets of lines can comprise first and second rounded jogs that are conformal to one another and which connect the first set of lines to the second set of lines.

Circuit interconnect structure

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Air gap spacer for metal gates

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Stressed material within gate cut region

A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Multilayer dielectric stack for damascene top-via integration

Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

Physical unclonable function

First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Nanosheet channel-to-source and drain isolation

A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

High aspect ratio buried power rail metallization

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Structure and process to tuck fin tips self-aligned to gates

A semiconductor device including a fin structure formed on a first semiconductor region, and a first semiconductor structure controlling the first semiconductor region, the first semiconductor structure formed on a substrate and spaced apart from the first semiconductor region including the fin structure.

Vertical transistor and method of forming the vertical transistor

Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.

Secure identification of wafer and chip

A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

Semiconductor device and method of forming the semiconductor device

A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

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Albany, NY, United States of America

Fee Li Lie