Stmicroelectronics S.r.l.

Micron Technology Incorporated

Sgs-thomson Microelectronics S.r.l.

Other

Intel Corporation

Stmicroelectronics S.a.

Co.ri.m.me-consorzio Per La Ricera Sulla Microelectronia Nel.

Federico Pio

Carlo Riva

Marco Sforzin

Paolo Amato

Graziano Mirichigni

Alessandro Orlando

Paola Zuliani

Enrico Gomiero

Paolo Ghezzi

Nicola Zatelli

Bruno Vajana

Livio Baldi

Giovanna Dalla Libera

Matteo Patelmo

Paola Paruzzi

Innocenzo Tortorelli

Carlo Cremonesi

Silvia Lucherini

Daniele Vimercati

Rino Micheloni

Marco Pasotti

Lorenzo Fratin

Raffaele Zambrano

Mathieu Pierre Lisart

Roberto Gastaldi

Efrem Bolandrina

Luca Crippa

Roberto Ravasio

Laurent Sourgen

Cesare Clementi

Roberta Bottini

Piero Capocelli

Alberto Modelli

Olivier Pizzuto

Gianbattsista Lo Giudice

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

Auto-referenced memory cell read techniques

Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

Systems and techniques for accessing multiple memory cells concurrently

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner.

Semiconductor packages with patterns of die-specific information

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) an indication positioned in a designated area of the first surface. The indication includes a code presenting information for operating the semiconductor die. The code is configured to be read by an indication scanner coupled to a controller.

Semiconductor packages with indications of die-specific information

A method for managing memory element failures in a memory subsystem is described. The method includes detecting, by the memory subsystem, a failed memory element in the memory subsystem and transmitting a redundant memory request based on detection of the failed memory element. The redundant memory request seeks to utilize memory storage in an external storage system in place of the failed memory element in the memory subsystem. Thereafter, the memory subsystem receives, from the external storage system, a redundant memory request confirmation, which indicates that the redundant memory request has been fulfilled and includes an address of a location in the external storage system. In response to receipt of the redundant memory request confirmation, the memory subsystem updates memory management information to map a logical address, which was previously mapped to the failed memory element, to the location in the external storage system.

Redundant cloud memory storage for a memory subsystem

Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first portion of the data block is accessed prior to the second portion of the data block during a read operation.

Nonvolatile storage using low latency and high latency memory

Growing community of inventors

Brugherio, Italy

Federico Pio