Inphi Corporation

Clariphy Communications, Inc.

Federico Nicolas Paredes

Oscar Ernesto Agazzi

Mario Rafael Hueda

Diego Ernesto Crivelli

Hugo Santiago Carrer

Norman L Swenson

Mauro Marcelo Bruni

Seyedmohammadreza Motaghiannezam

Damian Alfonso Morero

Vadim Gutnik

Paul Voois

Ramiro Rogelio Lopez

Martin Ignacio Del Barco

Jorge Manuel Finochietto

Matias German Schnidrig

Alfredo Javier Taddei

Elvio Adrian Serrano

Martin Carlos Asinari

Facundo Abel Alcides Ramos

Pablo Gustavo Quiroga

Roman Antonio Arenas

Alejandro Javier Schwoykoski

Adrián Ulises Morales

María Laura Ferster

Maria Laura Ferster

Ulises Morales

Laura Maria Ferster

A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

Timing recovery for optical coherent receivers in the presence of polarization mode dispersion

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Coherent transceiver architecture

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Growing community of inventors

Cordoba, Argentina

Federico Nicolas Paredes