Intel Corporation

Federico Ardanaz

Jonathan M Eastep

Richard J Greco

Jesus Corbal

Krishnakanth Venkata Sistla

Roger Gramunt

Asma Al-Rawi

Joel S Emer

Alan Beecher Kyker

Ian M Steiner

Nikhil Gupta

Roger Espasa

Ramkumar Nagappan

Geoff Lowney

Santiago Galan

Fuat Keceli

Toni Juan

Isaac Hernandez

Edward Thomas Grochowski

Ankush Varma

George Zacharias Chrysos

Ramacharan Sundararaman

Chunhui Zhang

Chung-Lun Chan

Kelly Livingston

Andrew J Herdrich

Chris MacNamara

Keith D Underwood

Vasudevan Srinivasan

Dennis Ryan Bradford

Dorit Shapira

Tozer J Bandorawalla

Yaxin Shui

Ujjwal Gupta

Micah Barany

Grant W McFarland

Ali Mohammad

Siddhartha Jana

Dmitry Lukianchenko

Stephanie Labasan

A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

Workload aware power limiting and multiple-input multiple-output control

Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.

Systems and methods for synergistic software-hardware power budget management

Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned 'weights' based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.

Hybrid prioritized resource allocation in thermally-or power-constrained computing devices

An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.

Dynamic maximum frequency limit for processing core groups

Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.

Techniques in performance and efficiency improvements of processors in a cooling system

Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.

System-wide network activity forecasting for performance improvement

Systems, apparatuses and methods may provide for determining, from a program comprising graphs of parallel operations and dependencies, an estimation of a droop risk associated with execution of the graphs by a load. A risk signal may be outputted based on the estimation. The risk signal may be associated with an adjustment in an output voltage of a voltage regulator and the output voltage is to be provided to the load.

Voltage droop mitigation technology in array processor cores

An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.

Power noise injection to control rate of change of current

Systems, apparatuses and methods may provide for receiving indicator data associated with activity of a load. Additionally, an estimation of a rate of change of a current of the load with respect to time may be determined from the indicator data. Moreover, a boost signal may be selectively output to a voltage regulator when the estimation of the rate of change is greater than a first amount. The boost signal may be associated with an adjustment in an output voltage of the voltage regulator and the output voltage may be provided to the load.

Accurate voltage control to enhance power performance of circuits

Hybrid prioritized resource allocation in thermally- or power-constrained computing devices

Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing a hybrid implementation where software running on CPU (Central Processing Unit, also referred to herein interchangeably as 'processor') cores performs more of the work for power management, enabling the PCU to remain as a simple or regular microcontroller. Other embodiments are also disclosed and claimed.

Hybrid power management approach

Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

Memory sequencing with coherent and non-coherent sub-systems

Systems, apparatuses and methods may provide for obtaining, by a system level reallocator in a plurality of reallocators arranged in a hierarchical tree, resource budget information. Additionally, application performance information may be obtained by at least one of the plurality of reallocators. Moreover, a performance imbalance between a plurality of compute subtrees associate with the application performance information may be reduced by the at least one of the plurality of reallocators and based at least in part on the resource budget information and the application performance information.

Mitigating load imbalances through hierarchical performance balancing

Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.

Processor power monitoring and control with dynamic load balancing

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Hillsboro, OR, United States of America

Federico Ardanaz