International Business Machines Corporation

Faye D Baker

Robert K Leidy

Edward J Nowak

Steven J Holmes

Robert J Gauthier, Jr

Steven H Voldman

Jeffrey Scott Brown

Albert Manhee Chu

Jason D Hibbeler

Robert J Allen

Daniel Nelson Maynard

Michael S Gray

Robert F Walker

Rock Nadeau

Mervyn Y Tan

Daniel Shaw Brooks

Anne Elizabeth McGuire

Casey Jon Grant

Mousa H Ishaq

Joel M Sharrow

Mark D Levy

Mark R Beckenbaugh

James D Weil

Jason J Freerksen

A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.

Variable performance ranking and modification in design for manufacturability of circuits

Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

IC layout optimization to improve yield

A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

Disclosed is a method of fabricating a semiconductor device, comprising: (a) providing a bare semiconductor substrate, the substrate having a frontside and a backside; (b) forming one or more protective films on the backside of the substrate; and (c) performing one or more wafer fabrication steps. Some or all the protective films may be removed and the method repeated multiple times during fabrication of the semiconductor device.

Backside protection films

The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

Method and structure to reduce latch-up using edge implants

According to the preferred embodiment, an erosion and dishing monitor and monitor method are provided that facilitates the accurate optimization of a planarization process as in semiconductor process. The dishing monitor comprises at least two monitor structure sets embedded in a semiconductor substrate, the monitor structure sets comprising a plurality of monitor structures connected together with a plurality of connective conductors. The erosion monitor comprises a plurality of elongated conductors embedded into a semiconductor substrate, the plurality of conductors having varying conductor widths and adjacent substrate widths.

Dishing and erosion monitor structure for damascene metal processing

According to the preferred embodiment, an erosion and dishing monitor is provided that facilitates the accurate optimization of a planarization process as in semiconductor process. The dishing monitor comprises at least two monitor structure sets embedded in a semiconductor substrate, the monitor structure sets comprising a plurality of monitor structures connected together with a plurality of connective conductors. The erosion monitor comprises a plurality of elongated conductors embedded into a semiconductor substrate, the plurality of conductors having varying conductor widths and adjacent substrate widths.

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Burlington, VT, United States of America

Faye D Baker