Micron Technology Incorporated

Intel Corporation

Lodestar Licensing Group LLC

Fatma Arzum Simsek-Ege

John David Hopkins

Krishna Kumar Parat

Srikant Jayanti

Jie Sun

Yuan He

Diem Thy N Tran

Haitao Liu

Suraj J Mathew

Vinay Nair

Raghunath Singanamalla

Akira Goda

Kamal M Karda

Mingdong Cui

Meng-Wei Kuo

Durai Vishak Nirmal Ramaswamy

Hongbin Zhu

Kris K Brown

Fawad Ahmed

Darwin Franseda Fan

Lavanya Sriram

Charles H Dennison

Kunal R Parekh

Scott James Derner

Richard Edward Fackenthal

Marsela Pontoh

Shruthi Kumara Vadivel

Gloria Yang

Deepti Verma

Pavan Kumar Reddy Aella

Chandra V Mouli

Luan C Tran

John A Smythe

Roger W Lindsay

Si-Woo Lee

Aaron R Wilson

Deepak Chandra Pandey

Yushi Hu

Zhenyu Lu

Purnima Narayanan

Brian J Cleereman

Aurelio Giancarlo Mauri

Trupti D Gawai

Prasanna Srinivasan

Anshika Sharma

James C Brighten

Brent Keeth

Gordon A Haller

Michael Amiel Shore

Christopher Gordon Wieduwilt

Baosuo Zhou

Guangyu Huang

Han Zhao

Farrell Martin Good

Eric Blomiley

Manuj Nahar

Randy J Koval

Beau D Barry

Steve V Cole

Nicholas R Tapias

Xiaolong Fang

Benben Li

Masihhur R Laskar

Toby D Robbs

Brian Dolan

Gitanjali T Ghosh

Shivani Srivastava

Yashvi Singh

Luoqi Li

Sharmila Velamur

Tanya Khatri

Yanni Wang

Daniele Vimercati

Thomas Arthur Figura

Kevin J Torek

Hongmei Wang

Ashonita A Chavan

Sanjeev Sapra

Terrence B McDaniel

Chiara Cerafogli

Yunfei Gao

Naveen Kaushik

Kathryn H Russo

Kamal Kumar Muthukrishnan

Rosa M Avila-Hernandez

Clement Jacob

Saurabh Keshav

Kangle Li

Carly M Wantulok

Sumana Adusumilli

Scott M Pook

Vivek Yadav

Yixin Yan

Irene K Thompson

Jessica M Maderos

Nirmal Ramaswamy

Jie Jason Sun

A microelectronic device comprises a periphery circuitry region, bank regions, a control circuitry structure, and a memory array structure. The periphery circuitry region comprises a central sub-region, and two arm sub-regions extending from the central sub-region from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length than the central sub-region in a second horizontal direction orthogonal to the first horizontal direction. The bank regions are horizontally outward of the periphery circuitry region. The control circuitry structure comprises relatively more speed-critical circuitry within a horizontal area of the periphery circuitry region, and relatively less speed-critical circuitry within horizontal areas of the bank regions. The memory array structure vertically underlies the control circuitry structure and comprises arrays of memory cells within the horizontal areas of the bank regions. Additional microelectronic devices and memory devices are also described.

Microelectronic devices and memory devices

Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

Word line drivers for multiple-die memory devices

Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Apparatuses including insulative structures of stack structures having different portions and related memory devices

A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures. The microelectronic device further comprises a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising a sub word line driver region comprising complementary metal-oxide-semiconductor (CMOS) circuits vertically overlying and within a horizontal area of the staircase structure, and conductive contact structures vertically extending between steps of the staircase structure and the sub word line driver region. Related memory devices, electronic systems, and methods are also described.

Memory devices and related electronic systems

An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

Memory arrays with vertical transistors and the formation thereof

A microelectronic device includes a first microelectronic device structure including a memory array region comprising memory cells and a second microelectronic device structure vertically overlying the first microelectronic device structure. The second microelectronic device structure includes control logic devices configured to effectuate at least a portion of control operations for the memory cells and first multi-capacitor structures within spaces between the control logic devices and horizontally neighboring at least one of the control logic devices. The first multi-capacitor structures span a same or fewer number of routing tiers as the control logic devices and are configured to regulate and supply voltage to one or more of the control logic devices.

Microelectronic devices, related electronic systems, and methods of forming microelectronic devices

A system may include a memory device, a computing device and a sensor. The memory device may include a first partition and a second partition. The first partition stores first data of a first user at a first security level. The second partition is configured to store second data of the first user at a second security level different from the first security level. The computing device may include at least one processor that implements a machine learning algorithm. The sensor may be configured to provide information to the computing device. The machine learning algorithm analyzes the information from the sensor to determine an occurrence of an event. Based on a determination of the occurrence of the event, the computing device provides access to at least one of the first data or the second data to a second user.

Event-based secured data access authorization system

A microelectronic device comprises a vertical stack of memory cells. The vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, a conductive pillar structure in electrical communication with the vertical stack of access devices, and an isolated conductive structure in electrical communication with a multiplexer comprising a vertically uppermost access device of the vertical stack of access devices. The microelectronic device further comprises a stack structure comprising conductive structures interleaved with insulative structures, at least some of the conductive structures individually in electrical communication with a memory cell of the vertical stack of memory cells and comprising a gate of an access device of the vertical stack of access devices. Related electronic systems and methods are also described.

A microelectronic device comprises vertical stacks of memory cells, each vertical stack of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure vertically extending through the vertical stack of access devices. The microelectronic device further comprises multiplexers and additional transistors vertically overlying the vertical stacks of memory cells, and global digit lines vertically overlying the multiplexer and the additional transistor. Related electronic systems and methods are also described.

A microelectronic device is disclosed including a control logic structure that includes sense amplifiers clustered around sense amplifier exit regions; an upper memory array structure underlying the control logic structure and that includes memory cells coupled to some of the sense amplifiers of the control logic structure by way of routing extending through the sense amplifier exit regions; and a lower memory array structure underlying the upper memory array structure and that includes additional memory cells coupled to some other of the sense amplifiers of the control logic structure by way of additional routing extending through the sense amplifier exit regions.

Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Methods, devices, and systems related to process control in manufacturing are described. In an example, a method can include receiving data from a first process control device affixed to a first manufacturing tool of a first type, identifying one or more attributes of the data via a second processing resource of a second process control device affixed to a second manufacturing tool of a second type different from the first type, determining one or more settings for the second manufacturing tool via the second processing resource in response to identifying the one or more attributes of the data, and sending a command including the one or more settings to the second manufacturing tool from the second process control device.

Process control device in manufacturing

A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

Microelectronic devices, and methods of forming microelectronic devices

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically overlying the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region configured to effectuate control operations for memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region and a second control logic device region configured to effectuate control operations for memory cells of the second memory array region. Related memory devices, electronic systems, and methods are also described.

Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

Transistor configurations for multi-deck memory devices

Growing community of inventors

Boise, ID, United States of America

Fatma Arzum Simsek-Ege