Micron Technology Incorporated

Intel Corporation

Fatma Arzum Simsek-Ege

John David Hopkins

Krishna Kumar Parat

Srikant Jayanti

Jie Sun

Yuan He

Diem Thy N Tran

Haitao Liu

Suraj J Mathew

Vinay Nair

Raghunath Singanamalla

Akira Goda

Kamal M Karda

Meng-Wei Kuo

Durai Vishak Nirmal Ramaswamy

Hongbin Zhu

Mingdong Cui

Kris K Brown

Fawad Ahmed

Lavanya Sriram

Charles H Dennison

Kunal R Parekh

Darwin Franseda Fan

Marsela Pontoh

Shruthi Kumara Vadivel

Deepti Verma

Gloria Yang

Pavan Kumar Reddy Aella

Chandra V Mouli

Luan C Tran

Scott James Derner

John A Smythe

Richard Edward Fackenthal

Roger W Lindsay

Si-Woo Lee

Aaron R Wilson

Yushi Hu

Deepak Chandra Pandey

Zhenyu Lu

Purnima Narayanan

Brian J Cleereman

Aurelio Giancarlo Mauri

Trupti D Gawai

Prasanna Srinivasan

Anshika Sharma

James C Brighten

Brent Keeth

Gordon A Haller

Michael Amiel Shore

Baosuo Zhou

Guangyu Huang

Han Zhao

Farrell Martin Good

Eric Blomiley

Randy J Koval

Beau D Barry

Xiaolong Fang

Benben Li

Brian Dolan

Gitanjali T Ghosh

Shivani Srivastava

Luoqi Li

Sharmila Velamur

Daniele Vimercati

Thomas Arthur Figura

Kevin J Torek

Hongmei Wang

Christopher Gordon Wieduwilt

Ashonita A Chavan

Terrence B McDaniel

Sanjeev Sapra

Manuj Nahar

Chiara Cerafogli

Yunfei Gao

Naveen Kaushik

Steve V Cole

Kathryn H Russo

Nicholas R Tapias

Toby D Robbs

Kamal Kumar Muthukrishnan

Rosa M Avila-Hernandez

Clement Jacob

Saurabh Keshav

Masihhur R Laskar

Kangle Li

Yashvi Singh

Carly M Wantulok

Sumana Adusumilli

Scott M Pook

Vivek Yadav

Yixin Yan

Tanya Khatri

Yanni Wang

Irene K Thompson

Jessica M Maderos

A microelectronic device comprises vertical stacks of memory cells, each vertical stack of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure vertically extending through the vertical stack of access devices. The microelectronic device further comprises multiplexers and additional transistors vertically overlying the vertical stacks of memory cells, and global digit lines vertically overlying the multiplexer and the additional transistor. Related electronic systems and methods are also described.

Microelectronic devices, related electronic systems, and methods of forming microelectronic devices

A microelectronic device is disclosed including a control logic structure that includes sense amplifiers clustered around sense amplifier exit regions; an upper memory array structure underlying the control logic structure and that includes memory cells coupled to some of the sense amplifiers of the control logic structure by way of routing extending through the sense amplifier exit regions; and a lower memory array structure underlying the upper memory array structure and that includes additional memory cells coupled to some other of the sense amplifiers of the control logic structure by way of additional routing extending through the sense amplifier exit regions.

Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Methods, devices, and systems related to process control in manufacturing are described. In an example, a method can include receiving data from a first process control device affixed to a first manufacturing tool of a first type, identifying one or more attributes of the data via a second processing resource of a second process control device affixed to a second manufacturing tool of a second type different from the first type, determining one or more settings for the second manufacturing tool via the second processing resource in response to identifying the one or more attributes of the data, and sending a command including the one or more settings to the second manufacturing tool from the second process control device.

Process control device in manufacturing

A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

Microelectronic devices, and methods of forming microelectronic devices

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically overlying the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region configured to effectuate control operations for memory cells of the first memory array region. The second microelectronic device structure comprises a second memory array region and a second control logic device region configured to effectuate control operations for memory cells of the second memory array region. Related memory devices, electronic systems, and methods are also described.

Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

Transistor configurations for multi-deck memory devices

Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

Word line drivers for multiple-die memory devices

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes multiple memory cells. Each memory cell may include a bottom electrode having an open top cylinder shape that contains a support pillar, may include a top electrode, may include an insulator that separates the top electrode from the bottom electrode, and may include a leaker device having an open top cylinder shape. A bottom surface of the leaker device may abut at least one of a top surface of the bottom electrode or a top surface of the support pillar. A top surface of the leaker device may abut a bottom surface of a conductive plate. The memory device may also include the conductive plate.

Memory device assembly with a leaker device

A microelectronic device is disclosed that includes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices and extending in a first direction; and word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and the word lines extend into word line exit regions. The word line exit regions are horizontally alternating with the array regions in the second direction; and sub word line driver sections are overlapping and above, and in electrical communication with the word line exit regions. Electrical communication between word lines in the word line exit regions and the sub word line driver sections vertically coupled with a vertical word line contact and other interconnections is laterally bounded within socket regions delineated by horizontal boundaries of the word line exit regions.

Microelectronic devices including control logic circuitry overlying memory arrays, and related memory devices and electronic systems

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

Microelectronic devices and electronic systems

Methods and non-transitory machine-readable media associated with treatment plan identification are described. Treatment plan identification can include receiving first signaling configured to monitor user health data and receiving second signaling configured to monitor user behavior data. Treatment plan identification can include writing data that is based at least in part on a combination of the first signaling and the second signaling and identifying output data representative of a treatment plan for the user based at least in part on input data representative of the written data and additional user data. Output data representative of the treatment plan can be transmitted to a computing device accessible by the user, a computing device accessible by a provider, or both.

Treatment plan identification

Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.

Fin field effect transistor sense amplifier circuitry and related apparatuses and computing systems

Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.

Global column repair with local column decoder circuitry, and related apparatuses, methods, and computing systems

Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Single-crystal transistors for memory devices

A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of the digit lines and the at least one of the contact structures, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

Memory devices including contact structures and related electronic systems

Growing community of inventors

Boise, ID, United States of America

Fatma Arzum Simsek-Ege