International Business Machines Corporation

Fatih Cilek

Michael V Koch

Matthias Ringe

Andreas H A Arp

Andreas Arp

Thomas Makowski

Andre Hertwig

Guenther Hutzl

Christian I Menolfi

Dieter Nissler

A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Burn-in resilient integrated circuit for processors

Embodiments are disclosed for routing a cell of a semiconductor chip, the cell being represented by a matrix, encoding first tracks of the cell as columns of the matrix and second tracks of the cell as rows of the matrix, respectively. The method includes performing a sweep operation on the matrix, the sweep operation including generating an index structure indexed by columns of the matrix, the index structure including information on candidate cut shapes that can be placed in a particular column of the matrix. Additionally, the method includes recursively placing cut shapes into the cell based on the index structure, one recursion of the placing including finding a possible cut shape and recursively placing the remaining cut shapes.

Routing a cell of a semiconductor chip

A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.

Yield improving leaf cells optimization for semiconductor netlists

An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

Calibrating internal pulses in an integrated circuit

According to one or more embodiments of the present invention, a computer-implemented method includes determining, for a first sector from multiple sectors of a clock mesh of a semiconductor circuit, a set of mesh wires. The method further includes generating tapping point candidates, selecting a first combination of tapping points, and performing an analog electrical simulation of a clock signal. The simulation includes feeding the clock signal into the clock mesh via the first combination of tapping points via a clock signal transmitter, and measuring delays for the clock signal to reach a set of measuring nodes. The maximum delay from the measured delays is selected, and, in response to the maximum delay being less than a previous delay value, the first combination of tapping points is used to connect sector buffers from the first sector to the clock mesh.

Optimally driving non-uniform clock mesh loads

Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Static compensation of an active clock edge shift for a duty cycle correction circuit

The present invention provides a system and method of correcting duty cycle (DC) and compensating for active clock edge shift. In an embodiment, the system includes at least one control circuit to receive DCC control signals and to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, at least one adjustment circuit to change a DC value of an input clock signal, at least one correction circuit to compensate for a shift of an active clock edge of the input clock signal, and where one of the at least one adjustment circuit and the at least one correction circuit is to receive the input clock signal and wherein one of the at least one adjustment circuit and the at least one correction circuit is to transmit a corrected output clock signal.

Correcting duty cycle and compensating for active clock edge shift

The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

Double compression avoidance

Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.

Skew control

Aspects of the present disclosure relate to adaptive mesh wiring. A clock signal is provided to a clock mesh area, wherein the clock mesh area includes a plurality of wires configured in a grid. A pair of loads with impermissible skew within the clock mesh area is identified based on a threshold value. A mesh network area partition enclosing the pair of loads with impermissible skew is determined. Modifications are then made to the mesh network area partition to attempt to reduce skew. In some embodiments, a wire width of a portion of wires included in the mesh network area partition is increased. In some embodiments, a wire is added in between two wires present in the mesh network area partition.

Adaptive clock mesh wiring

An apparatus of performing a clock skew adjustment between N clock signals. 2(N&#x2212;1) skew sensors are configured as successive pairs k, each pair k having a first skew sensor and a second skew sensor. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. A skew controller performs the clock skew adjustment based on the first and second information.

Method and apparatus for clock skew control with low jitter in an integrated circuit

A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

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Boeblingen, Germany

Fatih Cilek