Texas Instruments Corporation

Apple Inc.

University of Arkansas

Farzan Farbiz

Akram Ali Salman

Aravind Chennimalai Appaswamy

Amitava Chatterjee

Xiaoju Wu

James Paul Di Sarro

Gianluca Boselli

Ann Margaret Concannon

Thomas Hoffmann

Xin Yi Zhang

John Eric Kunz, Jr

Muhammad Yusuf Ali

Ali Mesgarani

Xianzhi Dai

Mansour Keramat

Zhong Yu Chen

Seyedeh Sedigheh Hashemi

Dusan Stepanovic

Ke Yun

Jaeduk Han

Praveen R Singh

Yang Xiu

A computer system may include multiple sensor circuits that monitor operation parameters of a computer system circuit in the computer system. A control circuit may use monitor signals generated by the sensor circuits to determine probabilities that the operation parameters are within corresponding ranges. The control circuit can use the determined probabilities to generate a combined probability, which can be compared to a threshold value. The operation of the computer system circuit can be adjusted by the control circuit using results of the comparison between the combined probability and the threshold value.

Control of computer system operation using sensor data

Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Semiconductor layout in FinFET technologies

A semiconductor controlled rectifier (FIG.A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region () having a first conductivity type (N) and a first heavily doped region () having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region () having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region () having the first conductivity type is formed within the second lightly doped region. A buried layer () having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region () having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

ESD protection circuit with isolated SCR for negative voltage operation

A sensor system included in an integrated circuit includes multiple sensor circuits and a control circuit. Using characterization data, a model may be generated that defines a relationship between measurable parameters of the integrated circuit and an operating characteristic of the integrated circuit. The control circuit can combine, using a function included in the model, data from the multiple sensor circuits to determine a value of the operating characteristic that is more accurate than a sensor circuit configured to measure a single parameter of the integrated circuit that varies with the operating characteristic.

Process-insensitive sensor circuit

An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.

High speed ESP protection circuit

An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.

Conductivity modulated drain extended MOSFET

Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.

ESD protection charge pump active clamp for low-leakage applications

A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor.

On-chip IEC ESD protection using parasitic PNP devices

A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

Growing community of inventors

Dallas, TX, United States of America

Farzan Farbiz