Fujitsu Corporation

Other

University of Southern California

Idelan, Inc.

Farzan Fallah

Massoud Pedram

Yazdan Aghaghiri

Toru Ishihara

Behnam Amelifard

Ehsan Pakbaznia

Indradeep Ghosh

Pranav N Ashar

Srinivas Devadas

Koichiro Takayama

Afshin Abdollahi

Anup Hosangadi

Tohru Ishihara

Ryan C Kastner

An input signal corresponding to an action other than a drag on any virtual keyboard causes an erroneous string having at least two characters with an incorrect character other than the last character to be displayed. A second input signal corresponding to a drag on a virtual keyboard triggers entry into an error correction mode. A first incorrect character is located, a corrected input is determined according to an angle and a slide direction of the first drag, and the layout and geometry of the virtual keyboard; the first incorrect character is replaced with the corrected input to provide and display a first corrected string. The replacement of the first incorrect character and the display of the first corrected string occur without input from any source external to the device other than the first and the second input signals.

Advanced methods and systems for text input error correction

A non-transitory program storage device having stored computer instructions that when executed cause one or more programmable control devices to: receive an input signal having at least one character to provide an erroneous string having at least one incorrect character; display the erroneous string having at least one incorrect character; accept an input signal which corresponds to a drag on a virtual keyboard from a key corresponding to an incorrect character on the virtual keyboard to a key corresponding to a corrected input on the virtual keyboard; replace the at least one incorrect character in the erroneous string with the corrected input to provide a corrected character string; and display the corrected character string.

A system for inputting data in an electronic device comprising: a segmented pattern on a touch sensitive graphical user interface; a numeric value associated to each of the segments; a set of the numeric values associated to at least one character to provide a corresponding character table stored in the electronic device; an input signal received on at least one segment to provide an input having numeric values; a sequence of at least one segment determined according to the input having numeric values and the character table; a matched character determined according to input having numeric values, the sequence and the character table; wherein the matched character is displayed on the touch sensitive graphical user interface of an electronic device, stored and the segmented pattern on the touch sensitive graphical user interface of the electronic device is reset.

Data entry systems and methods

Methods, devices and systems for moderating and policing voluntarily established transparency regarding past and present, and personal and professional relationships via online networking services. Identity of a person or commercial entity is verified before registration as a user. Each user is permitted a single profile. A profile includes a record of all relationships entered in the profile, some of which may be hidden by user. Each user is capable of linking his profile to profiles of other consenting users. Owner of a profile may flag inaccurate information on other linked profiles. The reliability or value of information in a profile is measured as a function of duration of existence of profile, transparency of the information in the profile, periods of inactivation, and number of times the profile is correctly flagged. A code is generated and used to allow gradual exposing of the profile of a user to his prospective contacts.

Computer based methods and systems for establishing trust between two or more parties

A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.

System and method for eliminating common subexpressions in a linear system

In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.

Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits

In one embodiment, a method for reducing power consumption at a cache includes determining a nonuniform architecture for a cache providing an optimum number of cache ways for each cache set in the cache. The nonuniform architecture allows cache sets in the cache to have associativity values that differ from each other. The method also includes implementing the nonuniform architecture in the cache to reduce power consumption at the cache. In another embodiment, the method also includes determining a code placement according to which code is writeable to a memory separate from the cache. The code placement reduces occurrences of inter cache-line sequential flows when the code is loaded from the memory to the cache. The method also includes compiling the code according to the code placement and writing the code to the memory for subsequent loading from the memory to the cache according to the code placement to further reduce power consumption at the cache.

Reducing power consumption at a cache

In one embodiment, a method for power mode transition in a multi-threshold complementary metal oxide semiconductor (MTCMOS) circuit includes clustering logic cells in the circuit to a number of logic clusters and optimizing wake-up times of the logic clusters to reduce a total turn-on time of the circuit while keeping below a predetermined threshold a sum of currents flowing from the circuit to ground, a sum of currents flowing from a supply voltage to the circuit, or both during a transition by the circuit from sleep mode to active mode.

Power mode transition in multi-threshold complementary metal oxide semiconductor (MTCMOS) circuits

In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The generation of the second object code takes into account one or more locations of one or more defects in a cache on a processor such that one or more instructions in the second object code are written only to nondefective locations in the cache.

Improving performance of a processor having a defective cache

In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

Setting threshold voltages of cells in a memory block to reduce leakage in the memory block

Techniques are provided for characterizing processor designs and estimating power consumption of software programs executing on processors. A power model of a processor may be obtained by performing simulation using one or more training programs to obtain average power consumption during one or more windows of operation, then using the results to select parameters and coefficients for a processor characterization equation that can estimate power consumption while minimizing error.

Estimating software power consumption

A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.

PG-gated data retention technique for reducing leakage in memory cells

In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.

Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits

A method and apparatus for generating processor test programs using a formal description of the processor's instruction set. An instruction set for a processor is formally described using a language such as ISDL. The formal description of the instruction set identifies certain characteristics of the instructions making up the instruction set. The formal description is combined with a test specification that describes desired properties of a test program by formally specifying test sequences that are to be applied to instructions having particular characteristics. A test program is generated by applying the formal test specification to the formal description of the instruction set including test sequences applicable to instructions having the particular characteristics.

Method and apparatus for test program generation based on an instruction set description of a processor

A method for reducing transitions on a bus is provided that includes receiving an input trace and constructing a Markov source correlating to the input trace. The method also includes identifying an encoding technique, which can either minimize or maximize an objective function associated with the input trace.

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San Jose, CA, United States of America

Farzan Fallah