Conexant, Inc.

Brooktree Broadband Holding, Inc.

Farshid Nowshadi

The present invention is directed to methods and systems for allocating bandwidth (or other shared resource) among multiple masters. According to an aspect of the present invention, an arbiter assigns a bucket to each CPU (or other device) where each bucket holds the credits for that CPU. Each bucket has a predetermined fill rate and a drain rate. Depending on the priority given to a particular CPU, the corresponding bucket will drain (or fill) at a particular rate. For example, CPUs with a higher priority will drain at a slower rate. For each clock tick (or other period of time) that a CPU is stalled, a number of credits is accrued. The bucket with the highest number of credits has priority and will be given access to the shared resource (e.g., DRAM, SDRAM, SRAM, EPROM, etc.).

Method and system for allocating bandwidth

A method and system is provided for interleaving multiple cycles streams from clients seeking SDRAM access. More particularly, a master scoreboard register is established for enabling the interleaving of many clients SDRAM access requests into a single stream optimized for maximum packing density of the different streams, thereby reducing the overhead associated with each individual stream. In one embodiment, at least one Master Score Board Register (MSBR) is provided for storing the order of cycles to go out of a controller/processor and to the SDRAM. If there is a set bit in a particular location in the MSBR then it means that the cycle is occupied and already allocated and cannot be used for anything else. If the bit is not set then the cycle that bit represents a vacant slot is ready for use by a client. Upon receipt of an SDRAM request, an interleaving engine identifies the bit locations in the MSBR associated with the requested cycles. It is then determined whether any of the requested bits are spoken for in the MSBR. If so, the client's command sequence is rejected for at least the present clock cycle and the MSBR is incremented and the requested bits are checked again during the next clock cycle.

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Beds, United Kingdom

Farshid Nowshadi