Cambridge Silicon Radio Limited

Qualcomm Incorporated

Farshid Nowshadi

David Chappaz

Steven James Wenham

John Bruce

Duncan Mcleod

In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.

Digital clock generation and variation control circuitry

A method of adjusting the transmission time of a signal in a radio link, the method being performed by a transmitter configured to transmit the signal over the radio link to a receiver and comprising the steps of ascertaining an accuracy that the receiver assumes for the transmitter's clock, calculating an assumed drift of the transmitter's clock based on the assumed accuracy of that clock and the time since a previous correlation between the transmitter's clock and the receiver's clock; and transmitting the signal at a time dependent on the assumed drift.

Transmission timing adjustment in radio systems

The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.

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Harston, United Kingdom

Farshid Nowshadi