Lsi Logic Corporation

Advanced Micro Devices Corporation

Ati Technologies Ulc

Farshad Ghahghahi

Aritharan Thurairajaratnam

Anand Govind

Leah Miller

Edwin M Fulcher

Milind S Bhagavat

Zafer S Kutlu

Lei Fu

Suming Hu

Arun Ramakrishnan

Andrew Kwan Wai Leung

Roden R Topacio

Kumar Nagarajan

Anwar Ali

Atila Mertol

Mohan R Nagar

Jeffrey A Hall

Leonard Mora

Zeki Z Celik

Yogendra Ranade

Jianguo Li

Nikon Banouvong

A carrier boat for die package flux cleaning, including: a body having at least one pair of substantially parallel sides, the body comprising one or more die package receptacles each oriented at a non-parallel angle relative to the substantially parallel sides of the body such that, when a die package is seated in a die package receptacle of the one or more die package receptacles, a first pair of opposing sides of a die of the die package are substantially perpendicular to the substantially parallel sides.

Carrier boat for die package flux cleaning

In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.

Semiconductor chip having stepped conductive pillars

An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

Integrated circuit product customizations for identification code visibility

Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

Multi-RDL structure packages and methods of fabricating the same

A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in first ordered channels of adjacent receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern. The first ordered channels are ordered to match an order of transmitter channels of a connector or another component on a printed circuit board to which the transmitter differential pairs are routed, and the second ordered channels are ordered to match an order of receiver channels of a connector or another component on a printed circuit board to which the receiver differential pairs are routed.

Ball grid array assignment

A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.

Robust high density substrate design for thermal cycling reliability

A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.

Ball assignment system

A flip chip substrate is provided, which includes a plurality of conductive layers, including a top layer and a bottom layer. A first plurality of contacts, including first and second contacts corresponding to a differential signal pair, are arranged on the top layer within a die bonding area. A second plurality of contacts, including third and fourth contacts corresponding to the differential signal pair, are arranged on the bottom layer. First and second traces are routed between the first and third contacts and between the second and fourth contacts, respectively, wherein the second trace is routed out of the die bonding area on a different layer than the first trace. The traces are routed in a manner that reduces the length difference between the traces.

Routing scheme for differential pairs in flip chip substrates

A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.

Substrate via layout to improve bias humidity testing reliability

A method for designing a routing pattern for electrical contacts on a printed circuit board by arranging contacts in an array of rows and columns on the printed circuit board, connecting groups of n columns of contacts to n&#x2212;1 columns of vias disposed interstitially between the contacts, thereby forming a vertical channel that does not extend completely through the contact array. Connecting the vias to traces, and routing the traces to an outside edge of the via array through the vertical channel. Connecting groups of n rows of the contacts to n&#x2212;1 rows of vias disposed interstitially between the contacts, thereby forming a horizontal channel that does not extend completely through the contact array, and intersects with the vertical channel. Connecting the vias to traces, and routing the traces to the outside edge of the via array through the horizontal channel.

Designing a ball assignment for a ball grid array package

A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.

Measurement of package interconnect impedance using tester and supporting tester

A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses. Because the major interior apertures does not need to be large enough to fit both the monolithic integrated circuit and the secondary circuit structure, there is more stiffener material available to provide structural support than there would be if the major interior aperture was large enough to fit both the monolithic integrated circuit and the secondary circuit structure.

Stiffener design

A printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n&minus;1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n&minus;1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.

Growing community of inventors

Los Gatos, CA, United States of America

Farshad Ghahghahi