Philips Electronics North America Corporation

Koninklijke Philips Corporation N.V.

Xilinx, Inc.

North American Philips Corporation

Sandia Corporation

Farrell Lynn Ostler

Gregory K Goodhue

Antoine Farid Dagher

Douglas E Thorpe

Ori K Mizrahi-Shalom

Charles E Dike

Santanu Roy

Neil Edward Birns

Edward A Burton

Ata R Khan

George Samuel Fleming

Kevin A Sholander

Techniques and mechanisms for performing dequeue operations for agents of a test bench environment. In an embodiment, a first group of agents are each allocated a respective ripe reservation and a second set of agents are each allocated a respective unripe reservation. Over time, queue management logic allocates respective reservations to agents and variously changes one or more such reservations from unripe to ripe. In another embodiment, an order of servicing agents allocated unripe reservations is based on relative priorities of the unripe reservations with respect to one another. An order of servicing agents allocated ripe reservations is on a first come, first served basis.

Method, apparatus and system for managing queue operations of a test bench environment

A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Circuit for and method of realigning data

A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes. In a preferred low-cost embodiment, a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions. Because cryptographic processes are characterized by operations on wide data items, particular emphasis is placed on the efficient processing of multi-word operations, including the use of constants having the same width as an instruction word. A simplified arithmetic unit is provided that efficiently supports the functions typically required for cryptographic operations with minimal overhead. A microcode-mapped instruction set is utilized in a preferred embodiment to facilitate multiple parallel operations in each instruction cycle and to provide direct processing control with minimal overhead.

Simple algorithmic cryptography engine

A processor architecture supports the decoupling of parameters typically associated with branch/jump instructions. Jump instructions are provided that do not contain an explicit destination address and other jump instructions are provided that do not contain an explicit test condition. The processing system provides a &ldquo;default&rdquo; value to any control element in the processor that is not expressly controlled by a particular instruction. In the case of a branch or call instruction, the default destination-address provided to effect the branch or call is the destination-address provided by a prior instruction. Subsequent or alternative branch or call instructions branch to this same address until the default address is set to a different address. In like manner, in most cases, the default condition that is used to determine the result of a conditional test, such as a conditional branch, call, or return instruction, is the last condition specified in a prior instruction.

Branch instructions with decoupled condition and address

A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie within specified bounds. When a &ldquo;circular increment&rdquo; or &ldquo;circular decrement&rdquo; instruction is executed that would cause the address to exceed a bound, the address is reset to the other bound. In a preferred embodiment, the programming instruction also sets condition flags that indicate when the address is at each bound. By providing these &ldquo;bounds&rdquo; flags in conjunction with the circular addressing operation, multiple-word data items can be processed efficiently. A base-address of N contiguous words in a memory is loaded into the circular register, and a circular addressing instruction is used to access each word of the N contiguous words in sequence; a bounds flag is set when the last word of the multi-word data item is accessed.

Circular address register

A microcontroller, which is configured in a certain mode, may generate signals that can cause malfunctions of the microcontroller or of other devices. For example, a prefetch cycle at an internal memory boundary may attempt to access external memory via a port when the port is connected to an I/O device. The system of the invention gates such signals and thus prevents possible damage to the microcontroller or peripheral device. In a preferred embodiment, a software programmable register is provided with one location dedicated to storing a bit. When that register bit is set, it prevents certain signals and address/data from appearing at the port and thus possibly causing harm to the microcontroller or a peripheral device connected to the port.

Software programmable bus disable system

A microcontroller with selectable function external pins. Program controllable configuration registers control pin function selection through multiplexers which select between data/address lines and special function unit output lines and which control line drivers which are disabled when the pins are used as input pins.

Pin selection system for microcontroller having multiplexer selects

An electronic device comprises a circuit that is provided with incrementally modifiable power consumption control means. By applying a program signal to this control means the balance between speed and power consumption is optimized. A PLA circuit considerably benefits from this architecture.

Electronic circuit with programmable gradual power consumption control

In a computer system, especially a microcontroller, a circuit for protecting hardware-modifiable status bits during a read-modify-write operation, which circuit is relatively simple to implement yet operates well and does not require an undue amount of die real estate to implement. The circuit comprises means for storing information representing whether a hardware-modifiable status bit has been updated during a read-modify-write operation, and means to prevent over-writing of the status bit during the write portion of the read-modify-write cycle when the stored information is detected. The means for storing the information comprises a latch set into its first state whose output indicates whether the first state exists. That output is connected to logic circuitry which blocks the rewrite portion of the read-modify-write operation from changing a hardware-modified bit set during that cycle.

System for write protecting a bit that is hardware modified during a

An instruction prefetch system for a digital processor, and in particular a microcontroller which includes the prefetch system and instruction queue normally provided as part of the instruction fetch unit, to which is added a second instruction prefetch buffer in the system, preferably in the bus interface unit which serves as the memory interface unit. This added prefetch buffer has storage for only a small number of bytes or words, and operates to supply prefetched instructions to the queue in the instruction fetch unit. However, it operates under the following constraint: it only prefetches within the boundaries of each small block of code memory and stalls when a block boundary is reached until a new address appears. This approach combines some cache and prefetch principles for a limited cost design.

Computer instruction prefetch system

A microcontroller which directly drives a memory with low order address bits during a fetch operation. Driving the low order address bits directly while the high order bits are latched during an address/data multiplex on the same pins allows the latch enable cycle to be skipped during sequential fetches. A sequential address detector indicates when the latch enable cycle can be skipped.

High speed memory access system for a microcontroller with directly

An arbiter provides at an output a priority signal that indicates which one of the input signals at an input has gained priority over all other ones. The arbiter comprises a signal processing path between the input and the output for determining the priority signal. The arbiter further comprises a control means coupled to the signal path for detecting (rare) conflicts among priority candidates. In response to the detected conflict, the control means generates control signals to modify the signal path. This conflict-solving part of the arbiter is located outside the signal path. Accordingly, a signal propagation delay in the path is largely independent of the number of input signals.

Arbiter with a direct signal path that is modifiable under

An arbiter based on pairwise mutual exclusion produces an absolute priority signal (G) indicating that one of three or more requests (R.sub.1, R.sub.2, . . . R.sub.N) has gained absolute priority over all the other. At least one mutual-exclusion element (20.sub.1 or 20p) in the arbiter is designed so that its pairwise priority determination car be reversed in response to at least one externally originated test signal (T.sub.1, T.sub.2 or T.sub.M-1, T.sub.M). By doing so after the requests have been asserted in a specified order, a priority conflict can be generated among the requests in order to check the conflict-resolution capability of the arbiter.

Growing community of inventors

Albuquerque, NM, United States of America

Farrell Lynn Ostler