Burroughs, Inc.

Other

National Semiconductor Corporation

Farooq M Quadri

Ananda H Kumar

Sidney J Schwartz

Ashish Asthana

Chung-Herng Hsin

This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices.

Methods for forming ceramic substrates with via studs

Disclosed is a bubble memory system that includes a plurality of bubble memory chips. Each of the chips have a number of minor loops, but only a predetermined portion of the loops are utilized to store information therein. The remaining loops may be defective and are not used. Data words that are to be stored in the bubble memory chips are passed through a first FIFO circuit which scrambles the bits in the words prior to their storage in the bubble memory chips. Due to this scrambling operation, no bits are stored in the defective loops. Data bits that are received from the bubble memory chips are passed thorugh a second FIFO circuit. There, all of the bits of each word are then realigned and presented at the FIFO output in parallel.

Bubble memory system having defective minor loops

A method of forming detector and dummy detector pair(s) of magnetoresistive elements on a bubble memory chip, with detector and dummy detector each having a balancing resistance network comprising parallel spaced apart end-connected lines of resistive material with the transverse legs (rungs) spaced between said parallel lines to form a ladder in-line (electrically) between the detector and pads for selectively balancing the pair(s), and for disconnecting certain rungs of the spaced apart end connected lines, if necessary, to change the path of current flow through the ladder and thus vary the resistance through the ladder. The product formed by the method comprises on-chip magnetoresistive detector element pair(s) including balancing resistance ladders, coupled in the current paths of the magnetoresistive elements, and having portions which can be selectively disconnected to change resistance of the ladder to balance the bridge network.

On-chip method of balancing memory detectors and balanced detectors

A bubble memory system comprising data chips each having a plurality of storage loops and wherein each is provided with additional storage loops to compensate for defective loops in the chip, and a control chip having control loops, one loop for each data chip and with bit positions corresponding in number to the number of storage loops in the data chip and connected to the data chip to prevent defective loops on the data chips from being utilized. Thus, data chips which would otherwise have been discarded as defective can now be used.

Bubble memory defect tolerant logic control circuit

A digital-to-analog converter utilizing magnetic domains with particular application to addressing large capacity bubble memory modules economically and with as short a delay as one cycle of rotation of the magnetic in-plane field including a plurality of storage loops and magnetoresistive sensors arranged in bridge networks to produce signals whose amplitude denote a weighted binary digit.

Magnetic bubble type D/A converter

An associative magnetic domain memory comprising; a predetermined number of storage loops having a predetermined number of magnetic elements on which domains circulate, said domains or absence of said domains on said magnetic elements in said storage loops representing bits of binary information; write-in section and read-out means disposed relative to said storage loops; said write-in section including, generator for generating bits and propagating said bits to positions adjacent said storage loops as a set of bits with a subset of said bits representing address bits and the rest of said set being data bits, and a gate for transferring said set of bits into said storage loops for storage therein; said read-out section including a replicator for forming replicas of sets of bits in said storage loops, a gate for transferring said replica sets one at a time, a sensor for receiving and sensing said transferred replica sets if one of said address bits does not match the desired address criteria. A plurality of similar memories are arranged in parallel with the replica address bits of each subset from each memory sensed as a row and an association performed on a plurality of address bit criteria. As before, the associative process will continue until there is a complete match of all the replica address bits with all the address criteria at which time the replica data associated with each of the replica address bits is read out.

Growing community of inventors

San Diego, CA, United States of America

Farooq M Quadri