University of Florida Research Foundation Inc

Farimah Farahmandi

Mark M Tehranipoor

Adib Nahiyan

Fahim Rahman

Andrew C Stern

Domenic J Forte

Shahin Tajik

Huanyu Wang

Mohammad Sazadur Rahman

Various embodiments provide methods, systems, computer program products, apparatuses, and/or the like for assessing vulnerability of an IC design to fault injection attacks, such as through a security property-driven vulnerability assessment framework for efficiently evaluating faults with respect to certain security properties associated with the IC design. In one embodiment, a method is provided. The method includes generating, using a fault-injection technique specification, one or more fault models describing attributes of one or more faults. The method further includes selecting, using the fault models and executable security properties associated with a design file of an IC design, a fault list identifying a plurality of possible faults for the IC design. The method further includes identifying, based at least in part on performing a fault simulation on the design file with the fault list, critical locations of the IC design. The method further includes implementing protections at the critical locations.

Security property-driven vulnerability assessments of ICs against fault-injection attacks

A method includes in part, generating an electro-optical frequency map (EOFM) of an active layer of an integrated circuit (IC), retrieving a reference map of the IC, comparing the EOFM of the IC with the reference map to determine whether there is a match between an intensity of an identified region in the EOFM map and an intensity of a corresponding region of the reference map, and detecting one or more hardware trojans in the IC if there is no match. The reference map may be associated with a layout of an IC known not to include hardware trojans. The reference map also may be a second EOFM associated with the IC. Alternatively, the reference map may be generated by applying power to the IC, and applying a clock signal to the IC.

Systems and methods for laser probing for hardware trojan detection

Methods, apparatus and computer program product for protecting a confidential integrated circuit design process. The computer-implemented method includes receiving a design specification dataset from a first untrusted computing device; extracting confidential design specification data from the design specification dataset; encrypting the confidential design specification data to produce encrypted confidential design specification data; generate a first encryption key to be associated with the encrypted confidential design specification data; retrieving a confidential design specification data subset for replacing a design element subset with a security hard macro (SHM) placeholder design element set; generating a security hard macro (SHM) placeholder feature set comprising those security hard macro (SHM) placeholder features representing mappings from the confidential design specification data subset to the SHM placeholder design element set; and transmitting, to the first untrusted computing device, the encrypted confidential design specification data, the first encryption key, and the SHM placeholder feature set.

Method, apparatus and computer program product for protecting confidential integrated circuit design

A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a &#x3c6;-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the &#x3c6;-bit protected Obfuscation Key generated by the LFSR, and output k&#x2514;&#x3c6;&#xd7;&#x3b1;&#x2518;-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.

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Gainesville, FL, United States of America

Farimah Farahmandi