Micron Technology Incorporated

Micron Quantum Devices Inc.

Xitore, Inc.

Batteroo, Inc.

Executive Advisory Firm LLC

Fariborz F Roohparvar

Michael S Briner

Mike Hossein Amidi

Ebrahim Abedifard

Mark A Hawes

Gregory L Cowan

Allahyar Vahidi Mowlavi

Farzan Bob Roohparvar

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

Apparatus, system, and method of byte addressable and block addressable storage and retrieval of data to and from non-volatile storage memory

Apparatus, system, and method of byte addressable and block addressable storage and retrival of data to and from non-volatile storage memory

Methods for extending the life of a battery output regulated voltages from output terminals configured to interface with input terminals of battery powered devices. A method includes receiving a battery electrical power output from the battery. The voltage output by the battery decreases from a battery first output voltage to a battery second output voltage during use of the battery. The electrical power output is used to drive a converter that outputs a converter electrical power having a converter output voltage greater than the battery second output voltage. The converter electrical power is output from output terminals configured to interface with input terminals of a battery powered device. The converter is configured and supported relative to the battery to interface with one or more output terminals of the battery.

Methods of extending the life of battery

A battery sleeve for extending the operational life of one or more batteries, the battery sleeve comprising a positive conductive electrode configured such that when the battery sleeve is coupled to at least one battery, the positive conductive electrode of the sleeve serves as the new positive terminal of the at least one battery.

Structure and method for extending battery life

A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.

Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells

A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory.

Method and apparatus for managing behavior of memory devices

A flash memory device is disclosed in which includes a plurality of flash memory transistors disposed within a doped well. The transistors are coupled at respective sources to an array ground node via a plurality of array ground lines. A plurality of switching devices distributed throughout the doped well switchingly couple the array ground lines to the doped well to reduce an elevated voltage otherwise present on the array ground lines when the array ground lines are heavily loaded.

Flash memory device with distributed coupling between array ground and substrate

An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like). In preferred embodiments, the test mode switch includes a set of series-connected pass transistors and a isolation voltage switch, the pass transistors pass test signals (indicative of test data to be written to or read from a selected cell) directly between the I/O pad and the selected cell in the test mode, and no signals pass through the pass transistors between the I/O pad and any memory cell in the normal mode. In the normal mode of such preferred embodiments, data to be written from the I/O pad to a selected cell passes through an input buffer before reaching the cell (or data to be read from a selected cell passes through an output buffer before reaching the I/O pad), and the isolation voltage switch holds a channel terminal of at least one of the pass transistors at a fixed supply voltage thereby preventing at least one of the pass transistors from undesirably switching on during the normal mode.

Memory circuit with switch for selectively connecting an input/output

A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are identical, are arranged in a pattern in which each two adjacent bits are different, or are arranged in another pattern, and wherein y is less than x. A method of testing an integrated circuit (IC) memory is also disclosed.

Output data compression scheme for use in testing IC memories

An integrated circuit selectively operable in either a first mode (consuming low power) or a second mode (consuming relatively high power). The circuit includes MOS transistors and a supply voltage circuit for at least one of the transistors. In both modes, the supply voltage circuit holds the body of each transistor at a fixed voltage (e.g., a voltage V.sub.CC in a range from 5 to 5.5 volts, where each transistor is a PMOS device). In the second mode the supply voltage circuit supplies this fixed voltage to the source of each transistor, but in the first mode it supplies a voltage equal to or slightly offset from the fixed voltage to the source of each transistor. In some embodiments, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to a well shared by a plurality of PMOS transistors, and a second voltage to the source of each PMOS device. Alternatively, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to the body of each of a plurality of NMOS transistors, and a second voltage to the source of each NMOS device. The second voltage is preferably offset from the first voltage by a voltage drop chosen to achieve a desired decrease in transistor leakage current in the first mode and a desired power up time for a transition from the first mode to the second mode. In preferred embodiments, the integrated circuit is a memory chip including a flash memory array, the voltage drop is in the range from 1.4 volts to 2 volts, and the voltage drop is implemented with one diode-connected MOS transistor or two diode-connected MOS transistors connected in series.

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Cupertino, CA, United States of America

Fariborz F Roohparvar