International Business Machines Corporation

Fariborz Assaderaghi

Jack Allan Mandelman

Louis L Hsu

Ghavam G Shahidi

Edward J Nowak

Heemyong Park

Rajiv V Joshi

Robert J Gauthier, Jr

Jed Hickory Rankin

Andres Bryant

Dominic Joseph Schepis

Louis Lu-Chen Hsu

Peter Edwin Cottrell

Lawrence F Wagner, Jr

Tze-Chiang Chen

Norman Jay Rohrer

K Paul Muller

Michael John Hargrove

Werner A Rausch

Peter I Smeys

Devendra K Sadana

Jeffrey P Gambino

Claude Louis Bertin

William R Tonti

John J Ellis-Monaghan

Jente Benedict Kuang

Randy William Mann

Stephen Larry Runyon

George E Smith, Iii

Timothy L Walters

Harold Wayne Chase

Steven H Voldman

Kerry Bernstein

Todd Alan Christensen

Anthony Gus Aipperspach

James A Culp

Ching-Te Kent Chuang

Dan Moy

Paul David Muench

Atul Champaklal Ajmera

Douglas Michael Dewanz

Bijan Davari

Mary Joseph Saccamango

Roy Childs Flaker

Mario M Pelella

Louis Lu-chen Hsu

Roy Childs Flaker, Deceased

Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.

SOI MOSFETS exhibiting reduced floating-body effects

A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to V.

Grounded body SOI SRAM cell

The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present invention, comprises the step of implanting neutral ions such as Ge or Ar into the source/drain regions. The implantation creates an amorphous silicon surface, and leaves a laterally extended amorphous layer under the spacer and a well defined amorphous/crystalline interface. The etch of silicon then extends laterally underneath the spacer, due to the higher etch rate of amorphous silicon and abrupt interface between amorphous and crystalline silicon.

Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon

A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.

Body contact MOSFET

A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.

T-RAM cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same

A method is provided for maximizing activation of a gate electrode while preventing source and drain regions from being excessively doped. The gate electrode is partially doped when exposed the source/drain implantation step. Then, the gate electrode is fully doped by the selective implantation step while the source/drain regions are blocked. Separate annealing steps are provided subsequent to the gate doping step and the source and drain implantation step.

CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions

A capacitor structure ( ) is implemented in an integrated circuit chip ( ) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body ( ) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions ( ) on both lateral sides of this device body ( ). These lateral regions ( ) are formed from a second semiconductor material. A dielectric layer ( ) is formed over both lateral regions ( ) and the device body ( ), while an anode layer ( ) is formed over the dielectric layer in an area defined by the device body. Each lateral region ( ) is coupled to ground at a first end ( ) of the elongated device body ( ). The anode ( ) is coupled to the chip supply voltage at a second end ( ) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Method for producing an integrated circuit capacitor

A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.

Memory array with dual wordline operation

A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc. which are connected to the T-RAM array.

T-RAM array having a planar cell structure and method for fabricating the same

A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

Ground-plane device with back oxide topography

A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to V .

A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Pair of FETs including a shared SOI body contact and the method of forming the FETs

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Mahopac, NY, United States of America

Fariborz Assaderaghi