Intel Corporation

Apple Inc.

Farhana Sheikh

Ram K Krishnamurthy

Sanu K Mathew

Jesse R Walker

Hossein Alavi

Markus Dominik Mueck

Shilpa Talwar

Hosein Nikopour

Feng Xue

Jaydeep P Kulkarni

Shu-Ping Yeh

Oner Orhan

Richard Dorrance

Vladimir Ivanov

Peter Sagazio

Yanjie J Wang

Junyoung Nam

Chia-Hsiang Chen

Ching-En Lee

Shreyas Sen

Anuja Surendra Vaidya

Ankit Sharma

Minyoung Park

Shay Gueron

Michael E Kounavis

Alexander W Min

Men Long

Stefano Pellerano

Scott J Weber

Alpa T Narendra Trivedi

Patrick Koeberl

Christopher Hull

Eduardo Alban

Erkan Alpman

Pramod Kolar

Ritesh Bhat

Karthik Subramanian

Wei-Hsiang Ma

Wei Tang

Subho Chatterjee

Albert Oskar Filip Andersson

Amy L Whitcombe

Sumeet Singh Nagi

Uneeb Yaqub Rathore

Alexios Konstantinos Balatsoukas Stimming

Shu-ping Yeh

Alexios Balatsoukas Stimming

A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.

Low power mmWave receiver architecture with spatial compression interface

Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.

Reconfigurable digital signal processing (DSP) vector engine

A spintronic device includes a first ferromagnetic layer. The first ferromagnetic layer includes a first direction of magnetic polarization. Furthermore, the spintronic device includes a second ferromagnetic layer. The second ferromagnetic layer includes a second direction of magnetic polarization opposite to the first direction. Furthermore, the spintronic device includes a long spin lifetime layer. Furthermore, the spintronic device includes a first tunnel barrier layer disposed between the first ferromagnetic layer and the long spin lifetime layer. Furthermore, the spintronic device includes a second tunnel barrier layer disposed between the second ferromagnetic layer and the long spin lifetime layer.

Spintronic devices, duplexers, transceivers and telecommunication devices

An orthogonalization matrix calculation circuit may include a scaling coefficient calculation circuit configured to calculate a scaling coefficient for each of a plurality of candidate update operations for the orthogonalization matrix, wherein each of the plurality of candidate update operations comprises combining linearly at least one of a first column or a second column of the orthogonalization matrix previously utilized to update the orthogonalization matrix, an update operation selection circuit configured to select an optimum candidate update operation from the plurality of candidate update operations, and a matrix update circuit configured to update the orthogonalization matrix according to the scaling coefficient of the optimum candidate update operation.

Lattice reduction-aided symbol detection

A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.

Fast Fourier transform architecture

A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.

Hybrid scheduling and latch-based pipelines for low-density parity-check decoding

The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.

Method and apparatus for dynamic radio emission compliance monitoring

In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

Capacitive wordline boosting

According to the present disclosure, a communication device configured to power on a main receiver to receive data from a network includes: a low power receiver configured to receive a wake up packet, including a preamble, from the network and oversample the wake up packet; a circuit arrangement including: a correlator configured to correlate the oversampled portion of the preamble; a delay and adder configured to take an output of the correlator, delay the output of the correlator, and add the output of the correlator back onto itself to produce a delay output; a peak detector configured to detect a peak pattern in the delay output; a demodulator configured to calculate a decoding threshold value to produce a demodulated data; and a packet parser configured to check the demodulated data for a data set in order to selectively output a nonzero signal to power on the main receiver.

Wake up radio device, circuit configuration, and method

An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the inputs associated with adaptive filters having taps, and determine correlation and cross-correlation data based thereon for a given iteration. The correlation data comprises a correlation matrix. Determining the matrix comprises determining submatrices in an upper triangular portion and a diagonal portion of the matrix. The accelerator comprises an adaptation core unit to determine adaptive weights associated with the adaptive filters, respectively, based on an adaptive algorithm, utilizing the correlation and cross correlation data. The accelerator unit comprises a convergence detector unit to determine a convergence parameter; and a controller to generate an iteration signal for each time interval based on the parameter. The iteration signal communicates to continue or conclude; the conclusion indicates determination of a final value of adaptive weights by the core unit.

RLS-DCD adaptation hardware accelerator for interference cancellation in full-duplex wireless systems

A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.

Energy efficient polynomial kernel generation in full-duplex radio communication

Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error.

Graphics lighting engine including log and anti-log units

A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.

Real-time blocker-adaptive broadband wireless receiver for low-power operation under co-existence in 5G and beyond

Growing community of inventors

Portland, OR, United States of America

Farhana Sheikh