Xilinx, Inc.

Sibercore Technologies, Inc.

Core Networks L.l.c.

Cisco Systems Inc.

Cortina Systems Corporation

Farhad Shafai

Kelvin Spencer

G F Randall Gibson

Gregory F Soprovich

Jason Coppens

Mark Andrew Gustlin

Jason Edward Podaima

Fredrik Olsson

Kenneth J Schultz

An apparatus consisting of a digital communication channel comprised of a multiplicity of lanes where data is striped across the lanes in a predefined sequence. Each lane has the ability to be powered down or powered up in response to the amount of data being held in a transmit buffer at one end of the communication channel. The method consists of monitoring the amount of data being held in the transmit buffer; making the decision of how many lanes are required based on the amount of data; sending signals to cause the required number of lanes to be powered down or powered up; and performing the required power down or power up action at the particular transmitter and receiver. The fill level of the transmit buffer is continually monitored and the required number of active lanes and the striping sequence is calculated and updated as required as a function of the fill level, where a larger amount of data waiting to be transmitted will result in a greater number of lanes being powered up and a smaller amount of data waiting to be transmitted will result in a lesser number of lanes being powered up.

Method and apparatus for adaptive power control in a multi-lane communication channel

A packet network interface apparatus includes a media access control (MAC) module for constructing a packet for transmission over a packet network and a physical coding sublayer (PCS) module for encoding the packet for transmission over a physical interface. An inter packet gap module located between the MAC module and the PCS module directly transfers data to the PCS module while maintaining a certain inter packet gap by deleting or inserting idle characters. The inter packet gap module has at least one memory module for temporary storage of packet data. The modules preferably operate in a common time domain.

Packet network interface apparatus and method

A method of creatine a CRC (Cyclic Redundancy Check) code for a data message in a data communications system includes sequentially placing portions of the data message on a bus of width W bits consisting of an integral number N of segments of width S. An initial portion of the message fills n complete segments, where n&#x3c;N. The method further includes processing the initial portion of the message placed on the bus to compute a CRC while compensating for any data on the bus preceding the initial portion, and subsequently processing one or more following portions of the message placed on the bus to update the CRC. A final portion of the message is processed to update the CRC by separately processing complete segments that do not fill the bus and any bytes that do not completely fill the last segment.

Method and apparatus for determining a cyclic redundancy check (CRC) for a data message

A method includes searching a content addressable memory based on a comparand. The comparand includes a collection of bits. A modified comparand is generated by modifying the comparand. The modified comparand is based at least in part on a comparand overlay data value. The content addressable memory is also searched with the modified comparand.

Searching a content addressable memory with modifiable comparands

An invention is provided for using a comparand provided to a CAM for multiple CAM operations without requiring the comparand to be reloaded from a host processor for each CAM operation. The invention includes a comparand data register that is capable of storing a comparand. Associated with the comparand data register, is a plurality of result registers. In operation, the comparand is provided as input data to the CAM for a plurality of search operations. For each search operation, the result is stored in one of the plurality of result registers. In this manner, the comparand stored in the data register can be reused for multiple search operations, with each result stored in a separate result register.

System and method for comparand reuse

Variable width Content Addressable Memory (CAM) devices for searching data of variable widths, are disclosed. The CAM devices include, a plurality of CAM blocks and a plurality of dual-mode first encoders. The plurality of CAM blocks is configured to store a plurality of data of variable widths with each data having one or more data portions of one or more predetermined widths. Each CAM block is configured to store a predetermined width portion of the data such that each data is stored in one or more CAM blocks. The CAM blocks receive a search data having a specified number of search data portions with each search data portion having one or more predetermined widths. Each CAM block receives a search data portion of the search data for searching the search data in the CAM blocks. The plurality of dual mode first encoders is configured for concatenating the specified number of the CAM blocks to generate one or more search results. A set of the dual mode first encoders concatenates the specified number of CAM blocks to match the width of the search data. The remaining dual mode first encoders generate one or more search results when the concatenated CAM blocks contain data that matches the search data.

Variable width content addressable memory device for searching variable width data

A three-port content addressable memory (CAM) device and method thereof are provided. The three-port CAM device includes a CAM, a search control block, and a maintenance control block. The CAM is configured to store data. The search control block is arranged to receive search data and search control signals via a first port for searching the search data in the CAM. The search control block is further configured to perform search operations by accessing the CAM. The search operations are performed within search cycles with each search operation being performed over multiple clock cycles. In this configuration, more than one search operations are capable of being performed simultaneously over one or more clock cycles. Search results of the search operations are output via a second port. The maintenance control block is configured to perform read/write operations by reading or writing specified data in the CAM via a third port.

Three port content addressable memory device and methods for implementing the same

The present invention provides a CAM circuit having a redundant array and method for implementing the same. The circuit includes a first CAM array, a redundant CAM array, one or more storage devices, a first encoder, and a redundant encoder. The first CAM array stores data and has a plurality of first entries. Each first entry has a plurality of first memory cells, wherein any first entry that includes one or more defective first memory cells is defective. The redundant CAM array has one or more redundant entries of redundant memory cells. Each of the one or more redundant entries has a redundant address and is associated with a defective first entry, wherein each redundant entry is configured store data for the associated first entry. The one or more storage devices associate each of the defective first entries with a redundant entry. The first encoder outputs a first search result from the first CAM array while the redundant encoder outputs a redundant search result from the redundant CAM array according to a specified algorithm.

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Kanata, Canada

Farhad Shafai