Xerox Corporation

Farhad D Rostamian

Louis D Mailloux

Hung M Pham

Rosario A Bracco

Daniel D Truong

Cathleen J Raker

Sue K Lam

Robert R Thompson, Jr

Cheryl A Pence

George L Harer

Hoan N Nguyen

Robert P Loce

David C Robinson

Michael Branciforte

Thomas Robson

James O Mitchel

A method and apparatus for the control of darkness/lightness in a digital image rendered by a printing system. The technique preferably employs templates to selectively apply different amounts of darkening (lightening) to borders of structures detected within the image dependent upon the need for darkening (lightening).

Method and apparatus for digital image darkness control using quantized fractional pixels

A system for providing an output from a digital printing apparatus which is of higher resolution than the native resolution of the original image data. For a given center pixel area, image data corresponding to pixel areas generally neighboring the center pixel area are attempted to be matched to various templates which are consistent with curved lines in which resolution enhancement of the center pixel would be desirable. In a second stage of template matching, a second set of image data, corresponding to pixel areas further away from the center pixel than the first set of pixel areas, is also attempted to be matched to templates. The second stage of template matching helps to avoid resolution enhancement of image data which is related to a halftone image.

Resolution enhancement for a digital printing apparatus

A lead edge lightening circuit which will lighten a scan line based on a seven by seven pixel area surrounding the current pixel. The area is divided into four sub-areas, each of four by four pixels, and each having the current pixel at one corner. Each sub-area is summed and compared to a threshold number. If the threshold number is equalled or exceeded by at least one of the four sums, an overlay bit, which can be white or black, is output. The current pixel is replaced by a white pixel if a white pixel has been output, otherwise the current pixel remains unchanged.

Quadrant-based density detection for lead edge lightening

This circuit for serializing n parallel data bits requires that the data clock, having a clock period T, be used to generate n phased clocks of the same frequency as the data clock, but varying in phase such that each phased clock is delayed T/n with respect to the previous one. This can be done using a digital phase locked loop device. These n phased clocks and n parallel data bits are then input to a logic circuit which uses an n input Register and an n input multiplexer to output one data bit for each phased clock. The result is a serializer that converts parallel data to serial data without the need for generating a higher frequency clock.

High speed serial interface between image enhancement logic and ros for

A circuit to be used just prior to the printing engine to improve the image quality of a raster output scanner by modifying the darkness, size or shape of the spot. A buffer holds a window of n by n image pixels, and compares the bit pattern to a set of templates. For each match, a correction number is output, each correction number being a gray scale, duty cycle or bit pattern to be used to correct the center pixel of the current window. The comparison logic, instead of comparing the entire set of bits in the window to the templates, uses a number of small logic blocks in parallel, each comparing a subset of bits from the window. The output from this first set of comparisons is substantially reduced from the original set. This reduced set is now input to a second logic block which generates the final correction output bits. By using two stages, the first stage being a number of smaller logic blocks, the speed of the process is increased and the number of parts and the complexity of the circuit is reduced

High speed pattern recognition technique for implementation of

Growing community of inventors

Los Angeles, CA, United States of America

Farhad D Rostamian