Advanced Micro Devices Corporation

Fares N Mubarak

Om P Agrawal

Kapil Shankar

Michele Young

A device having a number of general registers each allocated an input/output port and a number of internal 'buried' state registers. A user-controlled signal permits observation of the contents of the buried state registers at an input/output port although these registers are not allocated an input/output port. Each register is connected to a logic circuit internal to the device by a dedicated feedback path so that all registers can be used to specify states in a state machine sequencer. A fuse-programmable XOR gate permits a user to control generation of signals at the ports by permitting enabling and disabling of an inverting output buffer. Asynchronous reset and synchronous preset of the registers is provided. In addition to the dedicated feedback paths, programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an externasl pin. The input/output circuit can be deployed in banks, each bank selectably receiving the same or a different clock. The registers can be preloaded via an internally-generated signal or from the external pins. In an alternative embodiment, a programmable AND array and a pair of programmable OR arrays, each serving one of the banks, provides a flexible programmable logic array device with observable buried states.

Programmable logic device with observability and preloadability for

A logic circuit communicating to and from an input/output port in a variety of input modes and in a variety of output modes. The circuit may be configured to have a dedicated, registered, or latched input; and in the output mode to have a registered, combinatorial or latched output. A register/latch, in conjunction with a programmable input select multiplexer, can function as an input, output or buried register or as a transparent latch. A programmable clock select multiplexer selects between a clock/latch enable signal applied at an external pin or a product term generated internally. Clock polarity control is also provided. Asynchronous reset and preset of the register/latch is provided along with polarity control therefor. Dedicated and programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an external pin. The logic circuit can be deployed in banks, each bank electably receiving the same or a different clock. The register/latch can be preloaded via an internally-generated signal or from the external pins.

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San Jose, CA, United States of America

Fares N Mubarak