International Business Machines Corporation

Marvell Asia Pte., Ltd.

Faraydon Pakbaz

Sebastian Theodore Ventrone

Jack Robert Smith

Richard Stephen Graf

Stephen Dale Wyatt

Michael Richard Ouellette

Joseph Andrew Iadanza

Ram Kelkar

Pascal A Nsame

Keishi Okamoto

Ivan L Wemple

Ezra D B Hall

Amol Anil Joshi

Sanjay Upreti

Kurt A Carlsen

Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.

Tamper detection for a chip package

An integrated circuit includes logic regions and dynamically adjustable voltage controllers. A voltage controller connected to each logic region enables voltage adjustment while the chip is operating. Each voltage controller has a selector device connected to voltage input lines providing different voltages. A voltage sensor connected to the output of the selector device provides a supply voltage to one of the logic regions. A control circuit dynamically monitors the supply voltage, captures and stores a digital representation of the supply voltage during each cycle of a clock, and tracks variations over time, based on operation of the logic regions. When variations in the supply voltage exceed an operational threshold of one of the logic regions, the control circuit submits a request to a central controller. When the central controller grants permission, the control circuit dynamically adjusts the voltage by enabling the selector device to choose a different voltage input line.

Real-time adaptive voltage control of logic blocks

Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

Integrated circuit chip incorporating embedded thermal radiators for localized, on-demand, heating and a system and method for designing such an integrated circuit chip

An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone.

Input jitter filter for a phase-locked loop (PLL)

Disclosed are integrated circuits that incorporate an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. Specifically, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal.

Asynchronous circuit with an at-speed built-in self-test (BIST) architecture

Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.

Circuit and method for asynchronous pipeline processing with variable request signal delay

Designing integrated circuitry ('IC') includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.

Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry

A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects voltage variation waveforms below a minimum threshold value. Following this, an FDA is performed on the voltage variation waveforms below the minimum threshold value to create a set of frequency values. This involves performing an FFT on each of the voltage variation waveforms to obtain frequency domain data, wherein frequencies that cause a drop in voltage in the plurality of nodes are filtered. The method then sorts the frequency domain data, wherein the frequency domain data is arranged in order based on amplitude value, total power, frequency components, and/or amplitude of imaginary components.

Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis

A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.

Performance measurement of device dedicated to phase locked loop using second order system approximation

Disclosed is a method of allowing a user to assign I/O cells of an integrated circuit chip to package channels of a package, comprising: calculating package RLC values for each package channel in the package; and assigning each I/O cell to one or more package channels based on the calculated package RLC values of the package channels.

Growing community of inventors

Milton, VT, United States of America

Faraydon Pakbaz