Lattice Semiconductor Corporation

Fangquing Chu

Kai Zhou

Yu Shen

Kexin Luo

Zhi Wu

Shengguo Cao

Lingfen Yue

Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a fractional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL.

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Mountain View, CA, United States of America

Fangquing Chu