Fujitsu Corporation

Fang Yin

Yasuhiro Watanabe

Hirotaka Tamura

A data processing device including: a memory storing a plurality of values at a first time point, which include: values of state variables at the first time point and included in an evaluation function of a combinatorial optimization problem with a constraint condition; values of first local fields at the first time point and used to specify a change amount of values of the evaluation function by a change in the values of the state variables; and values of second local fields at the first time point and used to specify an amount to be added to the values of the evaluation function when the constraint condition is not satisfied; and a control circuit configured to return the plurality of state variables, the first local fields, and the second local fields to the values at the first time point when the determination circuit has determined not to accept the change.

Data processing device, computer-readable recording medium storing data processing program, and data processing method

A circular sign candidate extraction device includes: a memory; and a processor coupled to the memory, the processor being configured to perform processing, the processing including: detecting a circle from a captured image; specifying an annular region surrounded by the detected circle and a concentric circle, the concentric circle being a circle having a radius different from the detected circle; setting one or more pixels among pixels included in the annular region as determination pixels; and extracting a circular sign candidate from the detected circle in accordance with comparison between a color of the determination pixel and a predetermined color.

Circular sign candidate extraction device and non-transitory computer-readable storage medium for storing program

An image identification apparatus includes: a memory; and a processor coupled to the memory, the processor being configured to perform processing, the processing including: acquiring a contour image where pixels indicating a contour of a subject are extracted from an input image; detecting pixels of 3 points or more over the contour from each of regions in the contour image, which are separated by a predetermined distance in a vertical direction or a horizontal direction; calculating, for each combination of pixels of every 2 points among the detected pixels, an intersection point of a perpendicular bisector of a line segment having 2 points as end points and a distance between the intersection point and one of the detected pixels; and identifying, from the input image, a circle having the intersection point as a center of the circle and the distance as a radius.

Image identification apparatus, image identification method, and non-transitory computer-readable storage medium for storing image identification program

An apparatus includes a programmable circuit that configures circuits for executing tasks. The apparatus estimates an execution time-period required for executing a first task by first circuits configured in the programmable circuit, and determines a configuration number indicating a number of second circuits that are to be configured, in the programmable circuit, for executing a second task to be executed after the first task, based on the execution time-period and a configuration time-period required for configuring the configuration number of the second circuits in the programmable circuit. The apparatus causes the programmable circuit to configure, during execution of the first task, the configuration number of the second circuits, and adjusts the configuration number, based on a relationship between a time at which the first task is completed and a time at which configuration of the configuration number of the second circuits in the programmable circuit is completed.

Apparatus and method to configure an optimum number of circuits for executing tasks

An information processing device includes a processor configured to execute a program; and a programmable circuit device (a PLD hereafter) having a reconfiguration region in which a logic circuit requested in a configuration request from the processor is configured in response to the configuration request. The processor obtains measured values of data transfer rates of a plurality of logic circuits that are configured in the reconfiguration region and are operating; and on the basis of a sum of the obtained measured values of the data transfer rates, adjusts respective parallelisms of the plurality of logic circuits configured in the reconfiguration region, within a range ensuring that a sum of the data transfer rates does not exceed an upper limit of a data transfer rate of a bus provided in the PLD.

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Kawasaki, Japan

Fang Yin