Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Fang-Tsun Chu

Kvei-Feng Yen

Yao-Bin Wang

Wei Yu Ma

Kuo-Ji Chen

Yu-Cheng Chen

Chia-Hui Chen

Jiun-Jye Chang

Chen-Ming Chen

Wei-Yu Ma

Ta-Pen Guo

Cheng-Hung Tsai

Yung-Hui Yeh

Cheng-Chung Chen

Hung-Tse Chen

Chun-Yau Huang

Yong-Fu Wu

Chwan-Gwo Chyau

Jla-Xing Lin

A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics

An integrated circuit structure includes first and second integrated circuit devices disposed on a interposer. Each integrated circuit device has electrostatic discharge (ESD) protection circuitry therein connected to an internal ESD bus. The first and second integrated circuit devices communicate with one another through the interposer. The interposer includes an ESD bus electrically connected to the ESD busses of the first and second integrated circuit devices for providing cross-device ESD protection for the integrated circuit devices.

ESD protection for 2.5D/3D integrated circuit systems

The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

Semiconductor integrated circuit having a resistor and method of forming the same

An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage to a second power supply node. The second power supply voltage is lower than a first power supply voltage on the first power supply node. The ESD detection circuit is configured to activate the bias circuit to change working state in response to the ESD event. The ESD clamp further includes an LV ESD clamp coupled to the second power supply node, wherein the LV ESD clamp includes LV devices with maximum endurable voltages lower than the first power supply voltage.

ESD power clamp for high-voltage applications

A method for forming a poly-silicon film, using sequential lateral solidification (SLS) by laser irradiation through an optical device to pattern the laser beam and provide a periodic energy profile on the edges of transparent regions so as to widen the poly-silicon grains and achieve grain size uniformity. The optical device comprises a plurality of first transparent regions with a length of L, wherein at least one side of the edge of each of the first transparent regions has a first periodic shape.

Method for forming poly-silicon film

A method for electroplating low-resistance metal wire for resolving the problem to fabricate the metal wire on large-area substrate through the technology of photolithographing and etching in the prior art. Then the invention improves the RC-delay characteristic of circuit on large-area substrate and reduces the number of masks for processing of a structure of gate overlap lightly-doped drain (source) (GOLDD).

Method for electroplating metal wire

In the present invention, a method is used for forming a poly-silicon film that uses sequential lateral solidification (SLS) with two laser irradiations using a mask for patterning the laser beam so as to increase the grain length. The method also achieves enhancing the throughput due to the use of a mask that is designed for the method.

A mask for laser-crystallizing amorphous silicon into polysilicon is provided. The mask comprises a transparent substrate having a first block, a second block, and a third block with equal sizes. The second block is located between the first block and the third block. The first block includes a plurality of first transmission regions and a plurality of first opaque regions located between the first transmission regions. The second block includes a plurality of second transmission regions correspond to the first opaque regions and a plurality of second opaque regions located between the second transmission regions and corresponds to the first transmission regions. The third block includes a plurality of third transmission regions arranged corresponding to the centers of the first transmission regions and corresponding to centers of the second transmission regions and a plurality of third opaque regions located between the third transmission regions.

Method for crystallizing amorphous silicon into polysilicon and mask used therefor

A pixel array formed on a substrate mainly including scan lines and data lines is provided. The scan lines and the data lines are essentially consisted of conductive patterns disposed at different layers and contact windows electrically connected with the conductive patterns disposed at the different layers. The scan lines and the data lines are respectively consisted of conductive patterns to prevent the scan lines and the data lines from cracking when the substrate is warped. Besides, the pixel array further includes dielectric layers having trenches therein, to divide the dielectric layers into independent dielectric patterns. Thus, the dielectric layers would not crack easily when the substrate is warped.

Growing community of inventors

Taichung, Taiwan

Fang-Tsun Chu