National Central University

Fang-Ping Chou

Yue-Ming Hsin

Ching-Wen Wang

Guan-Yu Chen

Zi-Ying Li

A silicon photodiode with symmetry layout and deep well bias in CMOS technology is provided. The silicon photodiode includes a substrate, a deep well, and a PN diode structure. The deep well is disposed on the substrate, where an extra bias is applied to the deep well. The region surrounded by the deep well forms the main body of the silicon photodiode. The PN diode structure is located in the region surrounded by the deep well, where the silicon photodiode has a symmetry layout. The deep well is adopted when fabricating the silicon photodiode, and the extra bias is applied to the deep well to eliminate the interference and effect of the substrate absorbing light, and further greatly improve speed and bandwidth. Furthermore, the silicon photodiode has a symmetry layout, so that uniform electric field distribution is achieved, and the interference of the substrate noise is also reduced.

Si photodiode with symmetry layout and deep well bias in CMOS technology

A lateral avalanche photodiode structure including a substrate, a PN diode and a metal layer is provided. The substrate has at least one first electrode area, at least one light receiving area, and at least one second electrode area which are arranged horizontally. The first electrode area is also an avalanche area, and the light receiving area is between the first electrode area and the second electrode area. The PN diode is disposed in the substrate in the first electrode area. The metal layer is disposed on the substrate and covers the first electrode area and the second electrode area, but does not cover the light receiving area.

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Taipei, Taiwan

Fang-Ping Chou