Taiwan Semiconductor Manufacturing Comp. Ltd.

Fang-Lan Chu

Wei Cheng Wu

Harry-Hak-Lay Chuang

Ya-Chen Kao

Jui-Tsung Lien

Hong-Da Lin

Ku-Ning Chang

Yu-Chen Wang

Shih-Chang Liu

Wei-Cheng Wu

Li-Feng Teng

Nuo Xu

Yuan-Jen Lee

Harry-Haklay Chuang

In an embodiment, a method includes: receiving a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first grid of first magnetic features, the second wafer including a second alignment mark, the second alignment mark including a second grid of second magnetic features; aligning the first alignment mark with the second alignment mark in an optical alignment process; after the optical alignment process, aligning the first alignment mark with the second alignment mark in a magnetic alignment process, north poles of the first magnetic features being aligned with south poles of the second magnetic features, south poles of the first magnetic features being aligned with north poles of the second magnetic features; and forming bonds between the first wafer and the second wafer.

Wafer bonding method and bonded device structure

A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.

Integrated circuit structure and manufacturing method thereof

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

Test line letter for embedded non-volatile memory technology

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

Test line patterns in split-gate flash technology

The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology

The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.

Growing community of inventors

Taichung, Taiwan

Fang-Lan Chu