Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Fang Hong Gn

Liang Choo Hsia

Victor Seng Keong Lim

Rachel Yie Fang Wai

Lap Chan

Juan Boon Tan

Che-Chia Wei

Sajan Marokkey Raphael

Tak Yan Tse

Barbara Fong Chin Lim

Keng Heng Lai

Tanya Yang

Sekar Ramamoorthy

A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.

Defect monitoring in semiconductor device fabrication

A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.

Defect detection recipe definition

A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a defect programmed into the cell to facilitate defect detection.

Test chiplets for devices

A method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle in the wafer stepper. The wafer is polished by CMP. Thereafter, alignment mark positioning is checked for deviation from a normal vectorial position of the alignment mark whereby information about the deviation is fed back to the wafer stepper and wherein the wafer stepper automatically compensates for correctable alignment error based on the deviation information.

Accurate wafer patterning method for mass production

A method for fabricating an improved connection between active device regions in silicon, to an overlying metallization level, has been developed. The method produces contacts with superior and improved barrier integrity, which permits silicon device exposure to extended thermal process times and/or higher temperature processes without metal penetration into the silicon contact junction regions. The critical element is the addition of a conformal CVD tungsten layer in the multilayer barrier structure.

Semiconductor contact metallization

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Singapore, Singapore

Fang Hong Gn