International Business Machines Corporation

Fan Zhou

Yufei Li

Hao Yang

Cheng Song

Hou Gang Li

Liang Chen

Yang Liu

Bo Fan

Guofan Jiang

Yongfeng Pan

Zhi Gui Liu

The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Decoding method, decoding apparatus and decoder

Latency reduced error correction scheme with error indication function for burst error correction codes

A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.

Method, apparatus and decoder for decoding cyclic code

Embodiments of the present invention provide a method of computing validation coverage of an integrated circuit model, comprising: obtaining a logical structure of a integrated circuit model under validation; searching and recording signal paths in the integrated circuit model under validation based on the logical structure; and computing coverage of validation with respect to the signal paths. According to the technical solution as provided in the embodiments of the present invention, a signal path-based validation coverage may be obtained, thereby providing data regarding validation completeness more accurately.

Computing validation coverage of integrated circuit model

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Shanghai, China

Fan Zhou