Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoudnries Singapore Pte. Ltd.

Fan Zhang

Juan Boon Tan

Bei Chao Zhang

Liang Choo Hsia

Tae Jong Lee

Danny Pak-Chum Shum

Xiaomei Bu

Xinshu Cai

Laiqiang Luo

Pinghui Li

Yong Kong Siew

Wei Shao

Zhiqiang Teo

Fangxin Deng

Alex See

Soh Yun Siah

Wuping Liu

Tong Qing Chen

Haifeng Sheng

Kho Liep Chok

Jane Hui

Ming Zhu

Khee Yong Lim

Chim Seng Seet

Wenhe Lin

Yeow Kheng Lim

Young Way Teh

Dong Kyun Sohn

Daxiang Wang

Vincent Ho

Bo Tao

Danny PakChum Shum

Yew Tuck Clament Chow

Yong Chiang Ee

Vish Srinivasan

Luying Du

Shyue Seng Tan

Wei Liu

John Leonard Sudijono

Elgin Kiok Boone Quek

Darin A Chan

Yi Jiang

Wei Lu

Kin Leong Pey

Shao-fu Sanford Chu

Shaoqiang Zhang

Johnny Widodo

Lup San Leong

Tze Ho Simon Chan

Yiang Aun Nga

Mahesh Bhatkar

Jeffrey C Lam

Huey Ming Chong

Kian Ming Tan

Francis YongWee Poh

Huajun Liu

Aaron Chen

Wei Meng

Luona Goh

Victor Seng-Keong Lim

Dong Wang

Yee Mei Foong

Haiqing Zhou

Xian Bin Wang

Xin Qu

Shaoqing Zhang

Chian Yuh Sin

San Leong Liew

Pey Kin Leong

Sen Mei

Xingyu Chen

Cheng-Cheh Tan

Meng Luo

Yeon Kheng Lim

Jing Hui Li

Yu Jin Eugene Kong

Jun Chen

Jin Qiu Liu

Tian-Lin Chang

Lai Qiang Luo

Jianfang Liang

Xin Shu Cai

Eugene Kong

A memory cell including a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween, a floating gate including a first end over the channel region and a second end over the first doped region, a control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate, a word line overlapping the channel region, the first end of the floating gate, and the second portion the control gate, a first insulation member separating the floating gate, the control gate and the word line from the substrate; a second insulation member separating the floating gate from the control gate, and a third insulation member separating the floating gate and the control gate from the word line.

Memory cells with three-dimensional gate coupling and methods of forming thereof

The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.

Neuromorphic memories with split gate flash multi-level cell and method of making the same

Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.

Reliable non-volatile memory device

A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.

Control gate dummy for word line uniformity and method for producing the same

Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

Integrated magnetic random access memory with logic device

A semiconductor device with embedded non-volatile memory (eNVM) is described. The device is formed on a silicon-on-insulator (SOI) substrate, such as a fully depleted SOI (FDSOI) substrate. The substrate includes a SOI region and a hybrid region. The SOI region includes the surface substrate, BOX and bulk substrate while the hybrid region includes only the bulk substrate. NVM and high voltage (HV) transistors are disposed in the hybrid region while a logic and radio frequency (RF) transistors are disposed in the SOI region. The gates of the various transistors have about coplanar top surfaces. As such, the hybrid region compensates for height differential of transistors, enabling transistors to have about coplanar top surfaces. In addition, the hybrid region enables transistors which suffer from floating body effects to be disposed therein.

Embedded non-volatile memory (NVM) on fully depleted silicon-on-insulator (FD-SOI) substrate

Methods of fabricating integrated circuits and integrated circuits fabricated by those methods are provided. In an exemplary embodiment, a method includes providing a substrate having a first and second device wells, a gate dielectric overlying the first and second device wells, a first gate electrode layer overlying the gate dielectric, and a shallow trench isolation structure between the first and second device wells. An insulating dielectric layer is formed only partially overlying the first gate electrode layer. A second gate electrode material is deposited overlying at least the insulating dielectric layer to form a second gate electrode layer. The layers are patterned to form a second gate structure overlying the second device well. A contact is formed on the second gate electrode layer of the second gate structure with the contact overlying dielectric material of at least one of the insulating dielectric layer or the shallow trench isolation structure.

Integrated circuits with high voltage devices and methods for producing the same

A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.

Method to form thicker erase gate poly superflash NVM

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.

Integrated circuits having device contacts and methods for fabricating the same

Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Method for producing integrated circuit memory cells with less dedicated lithographic steps

Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures are provided. An exemplary integrated circuit includes a semiconductor substrate having a central semiconductor-on-insulator (SOI) region between first and second non-SOI regions. The substrate includes a semiconductor base in the SOI region and the non-SOI regions, an insulator layer overlying the semiconductor base in the SOI region, and an upper semiconductor layer overlying the insulator layer in the SOI region. The integrated circuit further includes a first conductivity type well formed in the base in the first region and in a first portion of the SOI region, and a second conductivity type well formed in the base in the second region and in a second portion of the SOI region lateral of the first conductivity type well. Also, the integrated circuit includes a non-volatile memory device structure overlying the upper semiconductor layer in the SOI region.

Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures

Integrated circuits and methods of producing the same are provide. In an exemplary embodiment, a method includes determining a memory area of the integrated circuit, and forming a select layer overlying the substrate. A portion of the select layer is selectively etched to form a select gate within the memory area. A concentration of an indicator is measured in an etch off-gas during the selective etching of the select layer, and the selective etching of the select layer is terminated when the concentration of the indicator crosses an end point determination concentration.

Integrated circuits with non-volatile memory and methods of producing the same

A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C, Cand C). The Ccomprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first Cplate is served by the gate electrode, a second Cplate is served by the substrate of the capacitor region and a Ccapacitor dielectric is served by the gate dielectric. The Cincludes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first Cplates and second group serves as second Cplates and the dielectric layers between the first and second groups serve as Ccapacitor dielectrics. The Cincludes a first Cplate served by the gate electrode, a second Cplate served by second group lines in the first metal level of the ILD layers, and a Ccapacitor dielectric is served by the first via level dielectric below Mand above the gate electrode. A first capacitor terminal is coupled to first capacitor plates of C, Cand Cand a second capacitor terminal is coupled to second capacitor plates of C, Cand C

3D high voltage charge pump

Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.

Reliable interconnect integration scheme

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposite within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.

Methods for fabricating integrated circuits having device contacts

Growing community of inventors

Singapore, Singapore

Fan Zhang