Broadcom Corporation

Ati Technologies Ulc

Fan Yeung

Roden R Topacio

Vincent K Chan

Sam Ziqun Zhao

Edward Law

Victor Fong

Nir Matalon

Raymond (Kwok Cheung) Tsang

Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).

Method and apparatuses for integrated circuit substrate manufacture

Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.

Semiconductor chip bump connection apparatus and method

Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or 'wishbone' shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.

I/O connection scheme for QFN leadframe and package structures

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Irvine, CA, United States of America

Fan Yeung