Petaio Inc.

Royole Corporation

Fan Yang

Changyou Xu

Lingqi Zeng

Peirong Ji

Yimin Chen

Jinxin Li

Aditi Rema Ganesan

Peichen Xu

Chao Jiang

Songling Yang

Cong Zhao

A PCIe architecture is disclosed incorporating a controller memory buffer (CMB). Write data is written to the CMB and is not read out for processing upon receiving a write command for the write data. The data is read out of the CMB and processed to obtain processed data upon receiving feedback from a NAND channel controller. The processed data may be written directly to the NAND channel controller or may be written to a light write buffer that is read by the NAND channel controller. The processed data may be written to a light write buffer functioning as a cut through buffer.

High bandwidth controller memory buffer (CMB) for peer to peer data transfer

Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.

Method for PRP/SGL handling for out-of-order NVME controllers

Example near-memory computing systems and methods are described. In one implementation, a system includes a host command processing system and a computational engine associated with a solid-state drive. In some situations, the computational engine includes multiple versatile processing unit slices coupled to one another. The multiple versatile processing unit slices are configured to perform different tasks in parallel with one another. The system also includes a host direct memory access module configured to access memory devices independently of a central processing unit.

Near-memory computing systems and methods

Example computational storage systems and methods are described. In one implementation, a storage drive controller includes a non-volatile memory subsystem to process multiple commands. Multiple versatile processing arrays are coupled to the non-volatile memory subsystem. The multiple versatile processing arrays can process multiple in-situ tasks. A host direct memory access module provides direct access to at least one memory device.

Computational storage systems and methods

Example storage control systems and methods are described. In one implementation, a storage drive controller includes a non-volatile memory subsystem that processes multiple commands. The storage drive controller also includes a controller memory buffer (CMB) memory management unit coupled to the non-volatile memory subsystem. The CMB memory management unit manages CMB-related tasks including caching and storage of data associated with the storage drive controller.

Command memory buffer systems and methods

A flow controller selects a direction (encryption/decryption) for an AES core according to quality of service parameters and a number of data words in encryption and decryption data buffers. A direction ratio may be calculated as a function of the quality of service parameters and the number of data words in the encryption and decryption data buffers. The flow controller selects the direction to reduce a cost function. The cost function may be at a minimum when a ratio of words in the encryption and decryption data buffers is the same as the direction ratio. A key management unit supplies keys according to the selected direction to the AES cores. Multiple AES cores may be used.

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Fremont, CA, United States of America

Fan Yang