Spansion Llc.

Cypress Semiconductor Corporation

Fan Wan Lai

Nian Niles Yang

Guowei Wang

Boon-Aik Ang

Yonggang Wu

Aaron Lee

Jiang Li

Zubin Patel

Alok Nandini Roy

Hongtau Mu

A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.

System and method for multi-layer global bitlines

A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage along with fast programming/erasure speeds and fast random access speeds.

Hybrid flash memory device

A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

Bitcell current sense device and method thereof

A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells () of a semiconductor memory device (). A high voltage generator () during program or erase operations provides a continuous high voltage level () on selected word lines () and maintains a continuous high voltage level supply to a bit line decoder () which sequentially provides the high voltage level () to a first portion of bit lines () and discharges () those bit lines () before providing the high voltage level to a second portion (). For additional improvements to program operations, the high voltage generator () decouples high voltages provided to the word lines () and the bit lines () by providing a current flow control device () therebetween and provides a boosting voltage at a time () to overcome a voltage level drop () resulting from a capacitor load associated with selected bit lines () and/or the bit line decoder () precharges () a second portion of the bit lines () while providing a high voltage level to a first portion to program () a first portion of memory cells (). For improvements to read operations, whether dynamic reference cells () are blank is determined by providing non-identically regulated high voltage levels from a first voltage source () to the dynamic reference cells () and from a second voltage source () to static reference cells () and, if the dynamic reference cells () are not blank, reads selected memory cells () by providing identically regulated high voltage levels to the selected memory cells (), the dynamic reference cells () and the static reference cells ().

Method and apparatus for high voltage operation for a high performance semiconductor memory device

Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.

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San Jose, CA, United States of America

Fan Wan Lai