Lucent Technologies Inc.

At&t Bell Laboratories

At+t Corp.

Agere Systems Inc.

Agere Systems Guardian Corp.

Fan Ren

Minghwei Hong

William Scott Hobson

Stephen J Pearton

James Robert Lothian

Joseph Petrus Mannaerts

Cammy R Abernathy

Alfred Yi Cho

Jueinai Raynien Kwo

Thomas R Fullowan

Young-Kai Chen

King Lien Tai

George J Zydzik

Utpal Kumar Chakrabarti

Dean Paul Kossives

Nitin J Shah

Donald Winslow Murphy

Melinda Lamont Schnoes

Jenn-Ming Kuo

Jenshan Lin

John Lopata

Adrian B Emerson

Matthias Passlack

The specification describes integrated circuit air isolated crossover interconnections designed for flip chip multi-chip module interconnection technology. The crossovers are made using a crossover interconnection substrate separate from the interconnection substrate of the integrated circuit. In one embodiment the integrated circuit is flip chip bonded to a multi-chip or multi-component interconnection substrate, and the crossover interconnections are made through solder bumps or balls soldered to a conductive layer on the crossover interconnection substrate. In another embodiment the crossover is made via a crossover substrate flip chip bonded to an integrated circuit mounted on a multi-chip or multi-component interconnection substrate.

Air isolated crossovers

Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or epitaxial re-growth, with gate oxide that is primarily Ga,O,, and with low midgap interface state density (e.g., at most 1&times;10,cm,eV,at 20&deg; C.). The method involves ion implantation, implant activation in an As-containing atmosphere, surface reconstruction, and in situ deposition of the gate oxide. In preferred embodiments, no processing step subsequent to gate oxide formation is carried out above 300&deg; C. in air, or above about 700&deg; C. in UHV. The method makes possible fabrication of planar enhancement-type MOS-FETs having excellent characteristics, and also makes possible fabrication of complementary MOS-FETs, as well as ICs comprising MOS-FETs and MES-FETs. The method includes deposition of gate oxide of overall composition Ga,A,O,, where Ga substantially is in the 3&plus; oxidation state, A is one or more electropositive stabilizer element adapted for stabilizing Ga in the 3&plus; oxidation state, x is greater than or equal to zero, z is selected to satisfy the requirement that both Ga and A are substantially fully oxidized, and y/(x&plus;y) is greater than 0.1.

Method of making an article comprising an oxide layer on a GaAs-based semiconductor body

The specification describes methods for making T-shaped metal gates for Schottky gate devices such as MESFETs and HEMTs. The method uses a bi-level photoresist technique to create a T-shaped feature for the gate structure. The metal gate is evaporated into the photoresist T-shaped feature and a lift-off process is used to remove unwanted metal. The photoresist is the dissolved away leaving the T-shaped gate. An important aspect of the process is the use of a plasma treatment of the first patterned resist level to harden it so that it is unaffected by the subsequent deposition and patterning of the second level resist.

Method of forming a T-shaped gate

A high quality oxide layer has been formed on a GaN surface by a method that involves preparation of the GaN such that the surface is essentially atomically clean and essentially atomically ordered, and that further involves exposing the surface to evaporant from a GGG (gallium gadolinium garnet) evaporation source. MOS structures comprising the GaN/oxide combination have shown low leakage current, as well as charge accumulation and depletion.

Article comprising an oxide layer on GAN

It has been found that a Ga-oxide-containing layer is substantially not etched in HF solution if the layer is a Ga-Gd-oxide with Gd:Ga atomic ratio of more than about 1:7.5, preferably more than 1:4 or even 1:2. This facilitates removal of a protective dielectric (typically SiO.sub.2) layer after an ohmic contact anneal, with the Ga-Gd-oxide gate oxide layer serving as etch stop and not being adversely affected by contact with the HF etchant. Gd-Ge-oxide also exhibits a composition-dependent etch rate in HCl:H.sub.2 O.

GaAs-based MOSFET, and method of making same

A high quality interface between a GaAs-based semiconductor and a Ga.sub.2 O.sub.3 dielectric an be formed if the semiconductor surface is caused to have less than 1% of a monolayer impurity coverage at completion of the first monolayer of the Ga.sub.2 O.sub.3 on the surface. This is achieved, for instance, by preparing the surface of a GaAs wafer under UHV conditions in a first growth chamber, transferring the wafer through a transfer module under UHV to a second growth chamber that is also under UHV, and growing the dielectric by evaporation of Ga.sub.2 O.sub.3 from a solid source, the process carried out such that the integrated impurity exposure of the surface is at most 100 Langmuirs. Articles according to the invention have low interface state density (&lt;10.sup.11 /cm.sup.2 .multidot.eV) and interface recombination velocity (&lt;10.sup.4 cm/s). Semiconductor/Ga.sub.2 O.sub.3 structures according to the invention can be used advantageously in a variety of electronic or optoelectronic devices, e.g., GaAs-based MOS-FETs, HBTs, lasers on solar cells.

Article comprising a gallium layer on a GaAs-based semiconductor, and

In a method of making a GaAs-based semiconductor laser, a fully processed wafer is cleaved, typically in the ambient atmosphere, into laser bars, the laser bars are loaded into an evacuable deposition chamber (preferably an ECR CVD chamber) and exposed to a H.sub.2 S plasma. Following the exposure, the cleavage facets are coated in the chamber with a protective dielectric (preferably silicon nitride) layer. The method can be practiced with high through-put, and can yield lasers (e.g., 980 nm pump lasers for optical fiber amplifiers) capable of operation at high power.

Method of making a GaAs-based laser comprising a facet coating with gas

A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.

Method of depositing thin passivating film on microminiature

In-containing III/V semiconductor materials (e.g., InGaP) can be dry etched in BCl.sub.3 in ECR apparatus. We have discovered that addition of N.sub.2 to the BCl.sub.3 can result in substantially higher etch rate (e.g., more than 50% higher). Etching is substantially without incubation period, and the resulting surface can be very smooth (e.g., RMS roughness less than 5 nm, even less than 2.5 nm). Exemplarily, the novel etching step is used in the manufacture of a InGaP/GaAs transistor.

Method of making in-containing III/V semiconductor devices

In accordance with the invention, aluminum-containing layers are grown by molecular beam processes using as an arsenic precursor phenylarsine (PhAs). Because PhAs is more reactive than arsine and less reactive than arsenic, it decomposes selectively on III-V surfaces but not on mask materials. Thus in contrast to conventional processes, growth using PhAs permits selective growth on unmasked gallium arsenide surfaces but inhibits growth on typical mask materials such as silicon nitride.

Method for selectively growing aluminum-containing layers

In accordance with the invention, gallium-containing layers are grown by molecular beam processes using as an arsenic precursor a compound of the dialkylaminoarsenic family (DAAAs) such as tris-dimethylamino arsenic (DMAAs). In contrast to conventional arsenic sources, DAAAs act as carbon 'getters'. When DAAAs are used as an arsenic source, the DAAAs getter carbon impurities from the gallium source. Thus, for example, DAAAs can be used as an arsenic source in combination with TMG as a gallium source to selectively grow high purity or n-type layers of gallium arsenide at low temperatures below 600.degree. C. In addition DMAAs has been found to be an excellent cleaning agent for gallium arsenide materials.

Method for selectively growing gallium-containing layers

The present applicants have discovered that a layer predominantly comprising tungsten can be formed into precise patterns having substantially vertical walls by using titanium as a mask and plasma etching in a fluorine-containing plasma such as CF.sub.4 or SF.sub.6. The success of the process is believed attributable to the occurrence of an etch stop reaction on the sidewalls of the tungsten. The products of the reaction inhibit horizontal etching. After the tungsten is etched, the titanium mask can be selectively removed, as by etching in dilute HF. Each step in the process can be effected without subjecting the workpiece to voltage magnitudes in excess of 200 volts or temperatures outside the range between room temperature and 200.degree. C.

Method for forming patterned tungsten layers

High carrier concentration, as well as abrupt change in such concentration in GaAs-based devices, is the consequence of selection of tin dopant-containing precursor compounds as used during layer growth. Alkyl tin compounds, as used during MetalOrganic Molecular Beam Epitaxy, are of particular value in the growth of pnp heterojunction bipolar transistors, likely in conjunction with other devices in large scale integrated circuits.

GaAs device fabrication utilizing metalorganic molecular beam epitaxy

Disclosed is a method of making semiconductor devices that comprises etching of a semiconductor layer, with a patterned metal layer acting as the etch mask. The patterned metal layer comprises a mask metal layer (exemplarily Ti) overlying a contact metal layer (exemplarily a Au-containing layer). In an exemplary embodiment the inventive method is used to manufacture InP-based heterojunction bipolar transistors.

Method of making semiconductor devices

This invention is concerned with the production of Schottky barrier gate contacts in MESFET devices. The contact is produced by wet-chemical removal of native oxide in a sealed inert gas ambient and blow-drying the wet-etched surface with the inert gas prior to deposition of gate electrode metal on GaAs by electron beam evaporation in an inert gas ambient. Use of Pt, due to its higher metal work function, as the gate contact metal results in a Schottky barrier height of 0.98 eV for Pt on n-type GaAs. This is considerably higher than the barrier height of conventionally processed TiPtAu contacts (0.78 eV). To lower the sheet resistivity of the gate contact, Pt is preferably used as a milti-layer contact in combination with metal having lower sheet resistivity, with Pt being in direct contact with the n-type GaAs surface, MESFETs fabricated using PtAu bilayer contacts show reverse currents an order of magnitude lower than TiPtAu-contacted companion devices, higher reverse breakdown voltages and much lower gate leakage. The use of this technology of native oxide removal and the PtAu bilayer contact provides a much simpler method of enhancing the barrier height on n-type GaAs than other techniques such as counter-doping the near-surface or inserting an interfacial layer.

Growing community of inventors

Warren, NJ, United States of America

Fan Ren