Via Alliance Semiconductor Co., Ltd.

Beijing University of Technology

Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Technologies, Inc.

Fan Jiang

Qiang Si

Shujun Chen

Liang Zhang

Chen Chen

Shen Li

Zhongding Liu

Jianxin Wang

Hui Wu

Guofeng Li

Minglu Xu

Jiajia Xia

Jinlong Gong

Guangqiang Men

Ning Huang

Xuping Wang

Zhenyang Lu

Ni Fu

A voltage regulator includes a first control circuit and a first voltage adjusting circuit. The first control circuit receives an output voltage and generates a first control signal according to the output signal. The first voltage adjusting circuit is coupled to the first control circuit, receives the first control signal, and adjusts the output voltage according to the first control signal.

Voltage regulator generating an output voltage according to a coupled load unit

A processing system and method for a data strobe signal (DQS). A counter circuit counts falling edges of the DQS within a valid region of the DQS and thereby generates a plurality of counting signals. An OR logic circuit receives the counting signals and a DQS window start signal and thereby generates a DQS window signal. A filter circuit is provided to gate the DQS according to the DQS window signal. The DQS window start signal is kept asserted until at least one of the counting signals changes due to the counting.

Processing system and method for data strobe signal

A controller includes an input/output circuit and a reference voltage generating circuit. The input/output circuit includes a plurality of receiving circuits. Each receiving circuit receives and processes one data bit and generates an output bit accordingly. The reference voltage generating circuit is coupled to the input/output circuit and includes a plurality of circuit units for providing a plurality of reference voltages. One of the circuit units is coupled to one of the receiving circuits to provide a reference voltage to the corresponding receiving circuit and the receiving circuit processes the data bit according to the received reference voltage.

Methods for generating reference voltages and controllers utilizing the same

A low-back-pressure penetrating arc welding apparatus and a welding method using the same are disclosed. Through vacuuming a central vacuum chamber of a low-back-pressure protection device by a suction device, a plume of a penetrating arc located in the central vacuum chamber, as well as a back side of a keyhole molten pool, are maintained in a negative-pressure vacuum state relative to an argon gas ambience. A pressure gradient in the keyhole molten pool is thus generated that points from a front side of the keyhole molten pool to the back side of the keyhole molten pool. The pressure gradient thus further enhances a stiffness of the front side of the keyhole molten pool as well as a stability of the penetrating arc, resulting in an enhancement in the piercing capability of the penetrating arc, without changing a force distribution and a temperature gradient of the keyhole molten pool.

Low back pressure penetrating arc welding apparatus and method

A delay lock loop including a selection unit, a delay unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit is coupled to the selection unit. The delay unit includes a delay factor and delays the first clock signal to generate a third clock signal according to the delay factor. The phase detection unit is coupled to the delay unit and the selection unit and generates the indication signal according to a phase difference between the second and third clock signals. The delay unit adjusts the delay factor according to the indication signal.

Delay lock loop

A delay lock loop is provided. A delay unit delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit generates an indication signal according to a phase difference between the second and fourth clock signals. When a duration of the indication signal being at a first level does not arrive at a pre-determined value and the indication signal is at a second level, the control unit increases the delay factor. When the duration of the indication signal being at the first level arrives at the pre-determined value and the indication signal is at the second level, the control unit reduces the delay factor.

A delay lock loop including a selection unit, a delay unit, an elimination unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit includes a delay factor and delays the first clock signal according to the delay factor to generate a third clock signal. The elimination unit is coupled to the selection unit and delays the second clock signal to generate a fourth clock signal. The phase detection unit is coupled to the delay unit and the elimination unit and generates the indication signal according to a phase difference between the third and fourth clock signals. The delay unit adjusts the delay factor according to the indication signal.

A delay lock loop is provided. A delay unit includes a delay factor and delays a first clock signal to generate a second clock signal according to the delay factor. An elimination unit delays a third clock signal to generate a fourth clock signal. A phase detection unit is coupled to the delay unit and the elimination unit and generates an indication signal according to a phase difference between the second and fourth clock signals. A control unit is coupled to the phase detection unit and the delay unit. The control unit controls the delay unit according to the indication signal to adjust the delay factor. When the delay factor is equal to an initial value, an initial time difference occurs between the first and second clock signals. A time difference between the third and fourth clock signals is equal to the initial time difference.

Gas metal arc welding (GMAW) is a widely used process for joining metals. Its main advantage over its competition gas tungsten arc welding (GTAW) is its high productivity in depositing metals. However, to melt metal from the wire to deposit into the work-piece, additional heat is consumed and applied to the work-piece with an uncontrolled fixed proportion to the effective heat that melts the wire. Such additional heat is often in excess of the needed heat input for the work-piece. The side-effects include a waste of the energy, an increased distortion, and possible materials property degradation. This invention is to device a method to transfer this part of heat to melt the wire by adding two wires, which form a pair of arc spots, under a tungsten arc. It also devices a method to assure the arc between the two wires be maintained stable such that the transfer be successfully continuous. The successful continuous transfer improves the energy efficiency, eliminates the adverse effects on the distortion and materials property, and decouples the controls on mass input and heat input on the work-piece.

Gas tungsten arc welding with cross AC arcing twin wires

For automatic initialization of a level shifter, an input signal in respect of a first voltage source is converted into a substantially zero voltage signal in response to an initial voltage derived from voltages of a first voltage source and a second voltage source when the second voltage source is activated but the first voltage source has not been activated yet. Afterwards, when the first voltage source and the second voltage source are both activated, the input signal in respect of the first voltage source is shifted into the output signal in respect the second voltage source without cooperation of the initial voltage.

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Beijing, China

Fan Jiang