Imagination Technologies Limited

Faizan Nazar

Sam Elliott

Kenneth C Rovers

Thomas Ferrere

Simon Gaulter

Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Method and system for verifying a sorter

An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.

Method and circuit for performing error detection on a clock gated register signal

An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.

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Hertfordshire, United Kingdom

Faizan Nazar